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([2a00:1fa0:603:a130:f42a:4975:5c69:31d3]) by smtp.gmail.com with ESMTPSA id y21sm975720ljm.25.2019.12.03.01.14.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 03 Dec 2019 01:14:37 -0800 (PST) Subject: Re: [PATCH 6/6] dt-bindings: spi: Document Renesas SPIBSC bindings To: Chris Brandt , Mark Brown , Rob Herring , Mark Rutland , Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Mason Yang References: <20191203034519.5640-1-chris.brandt@renesas.com> <20191203034519.5640-7-chris.brandt@renesas.com> From: Sergei Shtylyov Message-ID: <17e66541-41fb-26ed-c87b-15c59ab57bef@cogentembedded.com> Date: Tue, 3 Dec 2019 12:14:30 +0300 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <20191203034519.5640-7-chris.brandt@renesas.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hello! On 03.12.2019 6:45, Chris Brandt wrote: > Document the bindings used by the Renesas SPI bus space controller. > > Signed-off-by: Chris Brandt > --- > .../bindings/spi/spi-renesas-spibsc.txt | 48 +++++++++++++++++++ > 1 file changed, 48 insertions(+) > create mode 100644 Documentation/devicetree/bindings/spi/spi-renesas-spibsc.txt > > diff --git a/Documentation/devicetree/bindings/spi/spi-renesas-spibsc.txt b/Documentation/devicetree/bindings/spi/spi-renesas-spibsc.txt > new file mode 100644 > index 000000000000..b5f7081d2d1e > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/spi-renesas-spibsc.txt > @@ -0,0 +1,48 @@ > +Renesas SPI Bus Space Controller (SPIBSC) Device Tree Bindings > + > +Otherwise referred to as the "SPI Multi I/O Bus Controller" in SoC hardware > +manuals. This controller was designed specifically for accessing SPI flash > +devices. > + > +Required properties: > +- compatible: should be an SoC-specific compatible value, followed by > + "renesas,spibsc" as a fallback. > + supported SoC-specific values are: > + "renesas,r7s72100-spibsc" (RZ/A1) > + "renesas,r7s9210-spibsc" (RZ/A2) > +- reg: should contain three register areas: > + first for the base address of SPIBSC registers, > + second for the direct mapping read mode That's only 2 areas, not 3. :-) > +- clocks: should contain the clock phandle/specifier pair for the module clock. > +- power-domains: should contain the power domain phandle/specifier pair. > +- #address-cells: should be 1 > +- #size-cells: should be 0 > +- flash: should be represented by a subnode of the SPIBSC node, > + its "compatible" property contains "jedec,spi-nor" if SPI is used. Are any other flash variants supported? > + > +Example: > + > + spibsc: spi@1f800000 { > + compatible = "renesas,r7s9210-spibsc", "renesas,spibsc"; > + reg = <0x1f800000 0x8c>, <0x20000000 0x10000000 >; > + clocks = <&cpg CPG_MOD 83>; > + power-domains = <&cpg>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <40000000>; > + > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + partition@0000000 { > + label = "u-boot"; > + reg = <0x00000000 0x80000>; > + }; > + }; > + }; MBR, Sergei