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* [PATCH] arm64: dts: renesas: r8a77990: ebisu: Enable HS400 of SDHI3
@ 2019-01-10 14:28 Simon Horman
  2019-01-17 13:32 ` Simon Horman
  2019-01-17 13:54 ` Simon Horman
  0 siblings, 2 replies; 5+ messages in thread
From: Simon Horman @ 2019-01-10 14:28 UTC (permalink / raw)
  To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm, Simon Horman

Add SDHI3 UHS pin control and use it when enabling HS200 support
for SDHI3.

Based on work by Takeshi Kihara.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
Tested on top of renesas-devel-20190110-v5.0-rc1

[    2.967136] renesas_sdhi_internal_dmac ee160000.sd: mmc0 base at 0xee160000 max clock rate 200 MHz
[    3.055659] mmc0: new HS400 MMC card at address 0001
[    3.061726] mmcblk0: mmc0:0001 BGSD3R 29.1 GiB
[    3.070827] mmcblk0boot0: mmc0:0001 BGSD3R partition 1 16.0 MiB
[    3.077508] mmcblk0boot1: mmc0:0001 BGSD3R partition 2 16.0 MiB
[    3.084132] mmcblk0rpmb: mmc0:0001 BGSD3R partition 3 4.00 MiB, chardev (243:0)
[    2.967136] renesas_sdhi_internal_dmac ee160000.sd: mmc0 base at 0xee160000 max clock rate 200 MHz
[    3.055659] mmc0: new HS400 MMC card at address 0001
[    3.061726] mmcblk0: mmc0:0001 BGSD3R 29.1 GiB
[    3.070827] mmcblk0boot0: mmc0:0001 BGSD3R partition 1 16.0 MiB
[    3.077508] mmcblk0boot1: mmc0:0001 BGSD3R partition 2 16.0 MiB
[    3.084132] mmcblk0rpmb: mmc0:0001 BGSD3R partition 3 4.00 MiB, chardev (243:0)

[    2.901527] renesas_sdhi_internal_dmac ee160000.sd: Linked as a consumer to regulator.2
[    2.909824] renesas_sdhi_internal_dmac ee160000.sd: Linked as a consumer to regulator.1
[    2.967136] renesas_sdhi_internal_dmac ee160000.sd: mmc0 base at 0xee160000 max clock rate 200 MHz
[    3.055659] mmc0: new HS400 MMC card at address 0001
[    3.061726] mmcblk0: mmc0:0001 BGSD3R 29.1 GiB
[    3.070827] mmcblk0boot0: mmc0:0001 BGSD3R partition 1 16.0 MiB
[    3.077508] mmcblk0boot1: mmc0:0001 BGSD3R partition 2 16.0 MiB
[    3.084132] mmcblk0rpmb: mmc0:0001 BGSD3R partition 3 4.00 MiB, chardev (243:0)

128+0 records in
128+0 records out
134217728 bytes (134 MB) copied, 0.92438 s, 145 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 9.02486 s, 59.5 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 7.36003 s, 72.9 MB/s

512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 11.0156 s, 48.7 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 7.15907 s, 75.0 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 8.78869 s, 61.1 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 10.3861 s, 51.7 MB/s

The above test results seem favourable when compared to
testing against renesas-devel-20190110-v5.0-rc1 where the eMMC
device uses HS200 mode.

512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 14.7343 s, 36.4 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 8.46809 s, 63.4 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 14.6945 s, 36.5 MB/s

512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 19.1677 s, 28.0 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 21.3139 s, 25.2 MB/s
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 19.9205 s, 27.0 MB/s
---
 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 89383aa35d65..f2846c9eb83f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -535,6 +535,12 @@
 		power-source = <1800>;
 	};
 
+	sdhi3_pins_uhs: sd3_uhs {
+		groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
+		function = "sdhi3";
+		power-source = <1800>;
+	};
+
 	sound_pins: sound {
 		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
 		function = "ssi";
@@ -689,12 +695,13 @@
 &sdhi3 {
 	/* used for on-board 8bit eMMC */
 	pinctrl-0 = <&sdhi3_pins>;
-	pinctrl-1 = <&sdhi3_pins>;
+	pinctrl-1 = <&sdhi3_pins_uhs>;
 	pinctrl-names = "default", "state_uhs";
 
 	vmmc-supply = <&reg_3p3v>;
 	vqmmc-supply = <&reg_1p8v>;
 	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
 	bus-width = <8>;
 	non-removable;
 	status = "okay";
-- 
2.11.0


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] arm64: dts: renesas: r8a77990: ebisu: Enable HS400 of SDHI3
  2019-01-10 14:28 [PATCH] arm64: dts: renesas: r8a77990: ebisu: Enable HS400 of SDHI3 Simon Horman
@ 2019-01-17 13:32 ` Simon Horman
  2019-01-17 14:18   ` Wolfram Sang
  2019-01-17 13:54 ` Simon Horman
  1 sibling, 1 reply; 5+ messages in thread
From: Simon Horman @ 2019-01-17 13:32 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: linux-arm-kernel, Magnus Damm, Wolfram Sang, Niklas Söderlund

[CC Wolfram, Niklas]

On Thu, Jan 10, 2019 at 03:28:33PM +0100, Simon Horman wrote:
> Add SDHI3 UHS pin control and use it when enabling HS200 support
> for SDHI3.
> 
> Based on work by Takeshi Kihara.
> 
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> Tested on top of renesas-devel-20190110-v5.0-rc1

I would value a review of this patch.

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] arm64: dts: renesas: r8a77990: ebisu: Enable HS400 of SDHI3
  2019-01-10 14:28 [PATCH] arm64: dts: renesas: r8a77990: ebisu: Enable HS400 of SDHI3 Simon Horman
  2019-01-17 13:32 ` Simon Horman
@ 2019-01-17 13:54 ` Simon Horman
  1 sibling, 0 replies; 5+ messages in thread
From: Simon Horman @ 2019-01-17 13:54 UTC (permalink / raw)
  To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm

On Thu, Jan 10, 2019 at 03:28:33PM +0100, Simon Horman wrote:
> Add SDHI3 UHS pin control and use it when enabling HS200 support
> for SDHI3.
> 
> Based on work by Takeshi Kihara.
> 
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> Tested on top of renesas-devel-20190110-v5.0-rc1
> 
> [    2.967136] renesas_sdhi_internal_dmac ee160000.sd: mmc0 base at 0xee160000 max clock rate 200 MHz
> [    3.055659] mmc0: new HS400 MMC card at address 0001
> [    3.061726] mmcblk0: mmc0:0001 BGSD3R 29.1 GiB
> [    3.070827] mmcblk0boot0: mmc0:0001 BGSD3R partition 1 16.0 MiB
> [    3.077508] mmcblk0boot1: mmc0:0001 BGSD3R partition 2 16.0 MiB
> [    3.084132] mmcblk0rpmb: mmc0:0001 BGSD3R partition 3 4.00 MiB, chardev (243:0)
> [    2.967136] renesas_sdhi_internal_dmac ee160000.sd: mmc0 base at 0xee160000 max clock rate 200 MHz
> [    3.055659] mmc0: new HS400 MMC card at address 0001
> [    3.061726] mmcblk0: mmc0:0001 BGSD3R 29.1 GiB
> [    3.070827] mmcblk0boot0: mmc0:0001 BGSD3R partition 1 16.0 MiB
> [    3.077508] mmcblk0boot1: mmc0:0001 BGSD3R partition 2 16.0 MiB
> [    3.084132] mmcblk0rpmb: mmc0:0001 BGSD3R partition 3 4.00 MiB, chardev (243:0)
> 
> [    2.901527] renesas_sdhi_internal_dmac ee160000.sd: Linked as a consumer to regulator.2
> [    2.909824] renesas_sdhi_internal_dmac ee160000.sd: Linked as a consumer to regulator.1
> [    2.967136] renesas_sdhi_internal_dmac ee160000.sd: mmc0 base at 0xee160000 max clock rate 200 MHz
> [    3.055659] mmc0: new HS400 MMC card at address 0001
> [    3.061726] mmcblk0: mmc0:0001 BGSD3R 29.1 GiB
> [    3.070827] mmcblk0boot0: mmc0:0001 BGSD3R partition 1 16.0 MiB
> [    3.077508] mmcblk0boot1: mmc0:0001 BGSD3R partition 2 16.0 MiB
> [    3.084132] mmcblk0rpmb: mmc0:0001 BGSD3R partition 3 4.00 MiB, chardev (243:0)

I see the command lines for the tests were omitted below.
I have added them, for the record.

# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=128 iflag=direct
> 128+0 records in
> 128+0 records out
> 134217728 bytes (134 MB) copied, 0.92438 s, 145 MB/s
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=512 iflag=direct
> 512+0 records in
> 512+0 records out
> 536870912 bytes (537 MB) copied, 9.02486 s, 59.5 MB/s
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=512 iflag=direct
> 512+0 records in
> 512+0 records out
> 536870912 bytes (537 MB) copied, 7.36003 s, 72.9 MB/s
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=512 iflag=direct
> 512+0 records in
> 512+0 records out
> 536870912 bytes (537 MB) copied, 11.0156 s, 48.7 MB/s
>
# dd of=/dev/mmcblk0 if=/dev/zero bs=1M count=512 oflag=direct
> 512+0 records in
> 512+0 records out
> 536870912 bytes (537 MB) copied, 7.15907 s, 75.0 MB/s
# dd of=/dev/mmcblk0 if=/dev/zero bs=1M count=512 oflag=direct
> 512+0 records in
> 512+0 records out
> 536870912 bytes (537 MB) copied, 8.78869 s, 61.1 MB/s
# dd of=/dev/mmcblk0 if=/dev/zero bs=1M count=512 oflag=direct
> 512+0 records in
> 512+0 records out
> 536870912 bytes (537 MB) copied, 10.3861 s, 51.7 MB/s
> 
> The above test results seem favourable when compared to
> testing against renesas-devel-20190110-v5.0-rc1 where the eMMC
> device uses HS200 mode.
> 
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=512 iflag=direct
> 512+0 records in
> 512+0 records out
> 536870912 bytes (537 MB) copied, 14.7343 s, 36.4 MB/s
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=512 iflag=direct
> 512+0 records in
> 512+0 records out
> 536870912 bytes (537 MB) copied, 8.46809 s, 63.4 MB/s
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=512 iflag=direct
> 512+0 records in
> 512+0 records out
> 536870912 bytes (537 MB) copied, 14.6945 s, 36.5 MB/s
> 
# dd of=/dev/mmcblk0 if=/dev/zero bs=1M count=512 oflag=direct
> 512+0 records in
> 512+0 records out
> 536870912 bytes (537 MB) copied, 19.1677 s, 28.0 MB/s
# dd of=/dev/mmcblk0 if=/dev/zero bs=1M count=512 oflag=direct
> 512+0 records in
> 512+0 records out
> 536870912 bytes (537 MB) copied, 21.3139 s, 25.2 MB/s
# dd of=/dev/mmcblk0 if=/dev/zero bs=1M count=512 oflag=direct
> 512+0 records in
> 512+0 records out
> 536870912 bytes (537 MB) copied, 19.9205 s, 27.0 MB/s
> ---
>  arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
> index 89383aa35d65..f2846c9eb83f 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
> @@ -535,6 +535,12 @@
>  		power-source = <1800>;
>  	};
>  
> +	sdhi3_pins_uhs: sd3_uhs {
> +		groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
> +		function = "sdhi3";
> +		power-source = <1800>;
> +	};
> +
>  	sound_pins: sound {
>  		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
>  		function = "ssi";
> @@ -689,12 +695,13 @@
>  &sdhi3 {
>  	/* used for on-board 8bit eMMC */
>  	pinctrl-0 = <&sdhi3_pins>;
> -	pinctrl-1 = <&sdhi3_pins>;
> +	pinctrl-1 = <&sdhi3_pins_uhs>;
>  	pinctrl-names = "default", "state_uhs";
>  
>  	vmmc-supply = <&reg_3p3v>;
>  	vqmmc-supply = <&reg_1p8v>;
>  	mmc-hs200-1_8v;
> +	mmc-hs400-1_8v;
>  	bus-width = <8>;
>  	non-removable;
>  	status = "okay";
> -- 
> 2.11.0
> 

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] arm64: dts: renesas: r8a77990: ebisu: Enable HS400 of SDHI3
  2019-01-17 13:32 ` Simon Horman
@ 2019-01-17 14:18   ` Wolfram Sang
  2019-01-17 14:38     ` Simon Horman
  0 siblings, 1 reply; 5+ messages in thread
From: Wolfram Sang @ 2019-01-17 14:18 UTC (permalink / raw)
  To: Simon Horman
  Cc: linux-renesas-soc, linux-arm-kernel, Magnus Damm, Wolfram Sang,
	Niklas Söderlund

[-- Attachment #1: Type: text/plain, Size: 510 bytes --]

On Thu, Jan 17, 2019 at 02:32:17PM +0100, Simon Horman wrote:
> [CC Wolfram, Niklas]
> 
> On Thu, Jan 10, 2019 at 03:28:33PM +0100, Simon Horman wrote:
> > Add SDHI3 UHS pin control and use it when enabling HS200 support
> > for SDHI3.
> > 
> > Based on work by Takeshi Kihara.
> > 
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> > Tested on top of renesas-devel-20190110-v5.0-rc1
> 
> I would value a review of this patch.

Can you resend with the added CCs, please?


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] arm64: dts: renesas: r8a77990: ebisu: Enable HS400 of SDHI3
  2019-01-17 14:18   ` Wolfram Sang
@ 2019-01-17 14:38     ` Simon Horman
  0 siblings, 0 replies; 5+ messages in thread
From: Simon Horman @ 2019-01-17 14:38 UTC (permalink / raw)
  To: Wolfram Sang
  Cc: linux-renesas-soc, linux-arm-kernel, Magnus Damm, Wolfram Sang,
	Niklas Söderlund

On Thu, Jan 17, 2019 at 03:18:12PM +0100, Wolfram Sang wrote:
> On Thu, Jan 17, 2019 at 02:32:17PM +0100, Simon Horman wrote:
> > [CC Wolfram, Niklas]
> > 
> > On Thu, Jan 10, 2019 at 03:28:33PM +0100, Simon Horman wrote:
> > > Add SDHI3 UHS pin control and use it when enabling HS200 support
> > > for SDHI3.
> > > 
> > > Based on work by Takeshi Kihara.
> > > 
> > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > ---
> > > Tested on top of renesas-devel-20190110-v5.0-rc1
> > 
> > I would value a review of this patch.
> 
> Can you resend with the added CCs, please?

Sure, done.

^ permalink raw reply	[flat|nested] 5+ messages in thread

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Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-10 14:28 [PATCH] arm64: dts: renesas: r8a77990: ebisu: Enable HS400 of SDHI3 Simon Horman
2019-01-17 13:32 ` Simon Horman
2019-01-17 14:18   ` Wolfram Sang
2019-01-17 14:38     ` Simon Horman
2019-01-17 13:54 ` Simon Horman

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