* [PATCH] pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
@ 2019-01-11 11:50 Geert Uytterhoeven
2019-01-11 14:12 ` Simon Horman
2019-01-21 12:30 ` Geert Uytterhoeven
0 siblings, 2 replies; 3+ messages in thread
From: Geert Uytterhoeven @ 2019-01-11 11:50 UTC (permalink / raw)
To: Linus Walleij, Yoshihiro Shimoda
Cc: linux-renesas-soc, linux-gpio, Takeshi Kihara, Geert Uytterhoeven
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
MOD_SEL register bit numbering was different from R-Car D3 SoC and
R-Car H3/M3-[WN] SoCs.
MOD_SEL 1-bit H3/M3-[WN] D3
=============== ========== =====
Set Value = H'0 b'0 b'0
Set Value = H'1 b'1 b'1
MOD_SEL 2-bits H3/M3-[WN] D3
=============== ========== =====
Set Value = H'0 b'00 b'00
Set Value = H'1 b'01 b'10
Set Value = H'2 b'10 b'01
Set Value = H'3 b'11 b'11
MOD_SEL 3-bits H3/M3-[WN] D3
=============== ========== =====
Set Value = H'0 b'000 b'000
Set Value = H'1 b'001 b'100
Set Value = H'2 b'010 b'010
Set Value = H'3 b'011 b'110
Set Value = H'4 b'100 b'001
Set Value = H'5 b'101 b'101
Set Value = H'6 b'110 b'011
Set Value = H'7 b'111 b'111
This patch replaces the #define name and value of MOD_SEL.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 794a67117646 ("pinctrl: sh-pfc: Initial R8A77995 PFC support")
[shimoda: split a patch per SoC and revise the commit log]
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[geert: Use a macro to do the actual reordering]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested as we don't know how to test the impact of MOD_SEL bits on
output pins.
Using a macro makes the code easier to write, read, and maintain.
Use "git show --color-words" to see the difference.
I'd love to handle the reversal in the PINMUX_CFG_REG_VAR()
descriptions, but I can't use e.g. REV4(MOD_SEL0_24_23) there, as
MOD_SEL0_24_23 is a single parameter, not 4 parameters.
Can this be improved?
---
drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index 84d78db381e30249..9e377e3b9cb3c20c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -381,6 +381,9 @@ FM(IP12_23_20) IP12_23_20 \
FM(IP12_27_24) IP12_27_24 \
FM(IP12_31_28) IP12_31_28 \
+/* The bit numbering in MOD_SEL fields is reversed */
+#define REV4(f0, f1, f2, f3) f0 f2 f1 f3
+
/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
@@ -388,10 +391,10 @@ FM(IP12_31_28) IP12_31_28 \
#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
-#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) F_(0, 0)
-#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) F_(0, 0)
-#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) F_(0, 0)
-#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) F_(0, 0)
+#define MOD_SEL0_24_23 REV4(FM(SEL_PWM0_0), FM(SEL_PWM0_1), FM(SEL_PWM0_2), F_(0, 0))
+#define MOD_SEL0_22_21 REV4(FM(SEL_PWM1_0), FM(SEL_PWM1_1), FM(SEL_PWM1_2), F_(0, 0))
+#define MOD_SEL0_20_19 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
+#define MOD_SEL0_18_17 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
2019-01-11 11:50 [PATCH] pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering Geert Uytterhoeven
@ 2019-01-11 14:12 ` Simon Horman
2019-01-21 12:30 ` Geert Uytterhoeven
1 sibling, 0 replies; 3+ messages in thread
From: Simon Horman @ 2019-01-11 14:12 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Linus Walleij, Yoshihiro Shimoda, linux-renesas-soc, linux-gpio,
Takeshi Kihara
On Fri, Jan 11, 2019 at 12:50:20PM +0100, Geert Uytterhoeven wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> MOD_SEL register bit numbering was different from R-Car D3 SoC and
> R-Car H3/M3-[WN] SoCs.
>
> MOD_SEL 1-bit H3/M3-[WN] D3
> =============== ========== =====
> Set Value = H'0 b'0 b'0
> Set Value = H'1 b'1 b'1
>
> MOD_SEL 2-bits H3/M3-[WN] D3
> =============== ========== =====
> Set Value = H'0 b'00 b'00
> Set Value = H'1 b'01 b'10
> Set Value = H'2 b'10 b'01
> Set Value = H'3 b'11 b'11
>
> MOD_SEL 3-bits H3/M3-[WN] D3
> =============== ========== =====
> Set Value = H'0 b'000 b'000
> Set Value = H'1 b'001 b'100
> Set Value = H'2 b'010 b'010
> Set Value = H'3 b'011 b'110
> Set Value = H'4 b'100 b'001
> Set Value = H'5 b'101 b'101
> Set Value = H'6 b'110 b'011
> Set Value = H'7 b'111 b'111
>
> This patch replaces the #define name and value of MOD_SEL.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Fixes: 794a67117646 ("pinctrl: sh-pfc: Initial R8A77995 PFC support")
> [shimoda: split a patch per SoC and revise the commit log]
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> [geert: Use a macro to do the actual reordering]
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Untested as we don't know how to test the impact of MOD_SEL bits on
> output pins.
>
> Using a macro makes the code easier to write, read, and maintain.
> Use "git show --color-words" to see the difference.
>
> I'd love to handle the reversal in the PINMUX_CFG_REG_VAR()
> descriptions, but I can't use e.g. REV4(MOD_SEL0_24_23) there, as
> MOD_SEL0_24_23 is a single parameter, not 4 parameters.
>
> Can this be improved?
Likely but nothing springs to mind.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
2019-01-11 11:50 [PATCH] pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering Geert Uytterhoeven
2019-01-11 14:12 ` Simon Horman
@ 2019-01-21 12:30 ` Geert Uytterhoeven
1 sibling, 0 replies; 3+ messages in thread
From: Geert Uytterhoeven @ 2019-01-21 12:30 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Linus Walleij, Yoshihiro Shimoda, Linux-Renesas,
open list:GPIO SUBSYSTEM, Takeshi Kihara
On Fri, Jan 11, 2019 at 12:50 PM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> MOD_SEL register bit numbering was different from R-Car D3 SoC and
> R-Car H3/M3-[WN] SoCs.
>
> MOD_SEL 1-bit H3/M3-[WN] D3
> =============== ========== =====
> Set Value = H'0 b'0 b'0
> Set Value = H'1 b'1 b'1
>
> MOD_SEL 2-bits H3/M3-[WN] D3
> =============== ========== =====
> Set Value = H'0 b'00 b'00
> Set Value = H'1 b'01 b'10
> Set Value = H'2 b'10 b'01
> Set Value = H'3 b'11 b'11
>
> MOD_SEL 3-bits H3/M3-[WN] D3
> =============== ========== =====
> Set Value = H'0 b'000 b'000
> Set Value = H'1 b'001 b'100
> Set Value = H'2 b'010 b'010
> Set Value = H'3 b'011 b'110
> Set Value = H'4 b'100 b'001
> Set Value = H'5 b'101 b'101
> Set Value = H'6 b'110 b'011
> Set Value = H'7 b'111 b'111
>
> This patch replaces the #define name and value of MOD_SEL.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Fixes: 794a67117646 ("pinctrl: sh-pfc: Initial R8A77995 PFC support")
> [shimoda: split a patch per SoC and revise the commit log]
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> [geert: Use a macro to do the actual reordering]
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, queuing in sh-pfc-for-v5.1.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-01-11 11:50 [PATCH] pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering Geert Uytterhoeven
2019-01-11 14:12 ` Simon Horman
2019-01-21 12:30 ` Geert Uytterhoeven
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