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Date:   Wed, 23 Jan 2019 10:56:18 +0100
From:   Simon Horman <horms@verge.net.au>
To:     Geert Uytterhoeven <geert@linux-m68k.org>
Cc:     Geert Uytterhoeven <geert+renesas@glider.be>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Fabrizio Castro <fabrizio.castro@bp.renesas.com>,
        Biju Das <biju.das@bp.renesas.com>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        linux-clk <linux-clk@vger.kernel.org>
Subject: Re: [PATCH] clk: renesas: r8a774c0: Correct parent clock of DU
Message-ID: <20190123095617.vxbw3qnup4evjkj6@verge.net.au>
References: <20190121131410.21137-1-geert+renesas@glider.be>
 <CAMuHMdVt6kT30K2GTNU__B7px1O_N-oT-S_rLXi9MfngsrPHgg@mail.gmail.com>
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On Mon, Jan 21, 2019 at 02:15:07PM +0100, Geert Uytterhoeven wrote:
> On Mon, Jan 21, 2019 at 2:14 PM Geert Uytterhoeven
> <geert+renesas@glider.be> wrote:
> > According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
> > the parent clock of the DU module clocks on RZ/G2 is S1D1.
> 
> Oops, "RZ/G2E".

That aside,

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>