From: Simon Horman <horms@verge.net.au>
To: Wolfram Sang <wsa+renesas@sang-engineering.com>
Cc: linux-i2c@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH 2/2] i2c: rcar: refactor TCYC handling
Date: Wed, 23 Jan 2019 11:25:06 +0100 [thread overview]
Message-ID: <20190123102506.hi6tvyby5f4wbaho@verge.net.au> (raw)
In-Reply-To: <20190121170800.21144-3-wsa+renesas@sang-engineering.com>
On Mon, Jan 21, 2019 at 06:08:00PM +0100, Wolfram Sang wrote:
> The latest documentation made it clear that we need to initialize the
> TCYC value independently of DMA. Simplify the code to do that.
Hi Wolfram,
I see TCYC bit 6 is no longer used after this patch.
Does that warrant a mention in the changelog?
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
> drivers/i2c/busses/i2c-rcar.c | 15 ++++++---------
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
> index 4da7a1f6178b..48312f22094c 100644
> --- a/drivers/i2c/busses/i2c-rcar.c
> +++ b/drivers/i2c/busses/i2c-rcar.c
> @@ -39,8 +39,8 @@
> #define ICSAR 0x1C /* slave address */
> #define ICMAR 0x20 /* master address */
> #define ICRXTX 0x24 /* data port */
> -#define ICDMAER 0x3c /* DMA enable */
> -#define ICFBSCR 0x38 /* first bit setup cycle */
> +#define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */
> +#define ICDMAER 0x3c /* DMA enable (Gen3) */
>
> /* ICSCR */
> #define SDBS (1 << 3) /* slave data buffer select */
> @@ -83,7 +83,6 @@
> #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */
>
> /* ICFBSCR */
> -#define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */
> #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
>
>
> @@ -212,6 +211,10 @@ static void rcar_i2c_init(struct rcar_i2c_priv *priv)
> rcar_i2c_write(priv, ICMSR, 0);
> /* start clock */
> rcar_i2c_write(priv, ICCCR, priv->icccr);
> +
> + if (priv->devtype == I2C_RCAR_GEN3)
> + rcar_i2c_write(priv, ICFBSCR, TCYC17);
> +
> }
>
> static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
> @@ -363,9 +366,6 @@ static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
> /* Disable DMA Master Received/Transmitted */
> rcar_i2c_write(priv, ICDMAER, 0);
>
> - /* Reset default delay */
> - rcar_i2c_write(priv, ICFBSCR, TCYC06);
> -
> dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
> sg_dma_len(&priv->sg), priv->dma_direction);
>
> @@ -461,9 +461,6 @@ static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
> return;
> }
>
> - /* Set delay for DMA operations */
> - rcar_i2c_write(priv, ICFBSCR, TCYC17);
> -
> /* Enable DMA Master Received/Transmitted */
> if (read)
> rcar_i2c_write(priv, ICDMAER, RMDMAE);
> --
> 2.11.0
>
next prev parent reply other threads:[~2019-01-23 10:25 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-21 17:07 [PATCH 0/2] i2c: rcar: minor upporting from BSP Wolfram Sang
2019-01-21 17:07 ` [PATCH 1/2] i2c: rcar: comment maintenance Wolfram Sang
2019-01-23 10:23 ` Simon Horman
2019-02-05 13:33 ` Wolfram Sang
2019-01-21 17:08 ` [PATCH 2/2] i2c: rcar: refactor TCYC handling Wolfram Sang
2019-01-23 10:25 ` Simon Horman [this message]
2019-01-23 17:39 ` Wolfram Sang
2019-01-24 12:41 ` Simon Horman
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