Re: [PATCH v2] i2c: rcar: refactor TCYC handling

[Wolfram Sang <wsa@the-dreams.de>]

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On Tue, Feb 05, 2019 at 02:37:25PM +0100, Wolfram Sang wrote:
> The latest documentation made it clear that we need to initialize the
> TCYC value independently of DMA. The old code used TCYC06 (wrongly) for
> non-DMA transfers. The new code sets TCYC up independently from DMA.
> 
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>

The latter SoB shouldn't be there yet.

> ---
> 
> Change since v1: improve commit message per Simon's comment.
> 
>  drivers/i2c/busses/i2c-rcar.c | 15 ++++++---------
>  1 file changed, 6 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
> index 498ba4b87833..dd52a068b140 100644
> --- a/drivers/i2c/busses/i2c-rcar.c
> +++ b/drivers/i2c/busses/i2c-rcar.c
> @@ -39,8 +39,8 @@
>  #define ICSAR	0x1C	/* slave address */
>  #define ICMAR	0x20	/* master address */
>  #define ICRXTX	0x24	/* data port */
> -#define ICDMAER	0x3c	/* DMA enable */
> -#define ICFBSCR	0x38	/* first bit setup cycle */
> +#define ICFBSCR	0x38	/* first bit setup cycle (Gen3) */
> +#define ICDMAER	0x3c	/* DMA enable (Gen3) */
>  
>  /* ICSCR */
>  #define SDBS	(1 << 3)	/* slave data buffer select */
> @@ -83,7 +83,6 @@
>  #define TMDMAE	(1 << 0)	/* DMA Master Transmitted Enable */
>  
>  /* ICFBSCR */
> -#define TCYC06	0x04		/*  6*Tcyc delay 1st bit between SDA and SCL */
>  #define TCYC17	0x0f		/* 17*Tcyc delay 1st bit between SDA and SCL */
>  
>  
> @@ -212,6 +211,10 @@ static void rcar_i2c_init(struct rcar_i2c_priv *priv)
>  	rcar_i2c_write(priv, ICMSR, 0);
>  	/* start clock */
>  	rcar_i2c_write(priv, ICCCR, priv->icccr);
> +
> +	if (priv->devtype == I2C_RCAR_GEN3)
> +		rcar_i2c_write(priv, ICFBSCR, TCYC17);
> +
>  }
>  
>  static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
> @@ -363,9 +366,6 @@ static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
>  	/* Disable DMA Master Received/Transmitted */
>  	rcar_i2c_write(priv, ICDMAER, 0);
>  
> -	/* Reset default delay */
> -	rcar_i2c_write(priv, ICFBSCR, TCYC06);
> -
>  	dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
>  			 sg_dma_len(&priv->sg), priv->dma_direction);
>  
> @@ -461,9 +461,6 @@ static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
>  		return;
>  	}
>  
> -	/* Set delay for DMA operations */
> -	rcar_i2c_write(priv, ICFBSCR, TCYC17);
> -
>  	/* Enable DMA Master Received/Transmitted */
>  	if (read)
>  		rcar_i2c_write(priv, ICDMAER, RMDMAE);
> -- 
> 2.19.1
> 

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