From: Simon Horman <horms@verge.net.au>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Biju Das <biju.das@bp.renesas.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Magnus Damm <magnus.damm@gmail.com>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Chris Paterson <Chris.Paterson2@renesas.com>,
Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Subject: Re: [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support
Date: Thu, 7 Feb 2019 11:43:06 +0100 [thread overview]
Message-ID: <20190207104305.tchwfqwqxysum4la@verge.net.au> (raw)
In-Reply-To: <CAMuHMdVeVV9d4Sf=iPQ2UCrGqrnsh2Y9QCWaupwKc7QmRhCebw@mail.gmail.com>
On Thu, Feb 07, 2019 at 11:13:03AM +0100, Geert Uytterhoeven wrote:
> On Thu, Feb 7, 2019 at 9:37 AM Biju Das <biju.das@bp.renesas.com> wrote:
> > Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges
> > mapping for pciec0 node. Also declare pcie bus clock, since it is
> > generated on the CAT874 main board.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied for v5.1.
prev parent reply other threads:[~2019-02-07 10:43 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-07 8:31 [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support Biju Das
2019-02-07 8:31 ` [PATCH 2/2] arm64: dts: renesas: cat875: Enable PCIe support Biju Das
2019-02-07 10:13 ` Geert Uytterhoeven
2019-02-07 10:43 ` Simon Horman
2019-02-07 10:13 ` [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support Geert Uytterhoeven
2019-02-07 10:43 ` Simon Horman [this message]
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