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From: Simon Horman <horms@verge.net.au>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
	Takeshi Kihara <takeshi.kihara.df@renesas.com>
Subject: Re: [PATCH 5/5] clk: renesas: rcar-gen3: Rename DRIF clocks
Date: Fri, 29 Mar 2019 10:39:36 +0100	[thread overview]
Message-ID: <20190329093936.znco6mrqslngn7ai@verge.net.au> (raw)
In-Reply-To: <20190327124140.8800-6-geert+renesas@glider.be>

On Wed, Mar 27, 2019 at 01:41:40PM +0100, Geert Uytterhoeven wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> 
> According to the R-Car Gen3 Hardware Manual Errata for Rev. 1.50 of Feb
> 12, 2019, the DRIF clocks have been renamed as follows:
> 
>     DRIF0 to DRIF00
>     DRIF1 to DRIF01
>     DRIF2 to DRIF10
>     DRIF3 to DRIF11
>     DRIF4 to DRIF20
>     DRIF5 to DRIF21
>     DRIF6 to DRIF30
>     DRIF7 to DRIF31
> 
> Therefore, this patch renames the DRIF clock names from DRIFn to DRIFmm.
> 
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

> ---
>  drivers/clk/renesas/r8a7795-cpg-mssr.c  | 18 +++++++++---------
>  drivers/clk/renesas/r8a7796-cpg-mssr.c  | 16 ++++++++--------
>  drivers/clk/renesas/r8a77965-cpg-mssr.c | 17 +++++++++--------
>  drivers/clk/renesas/r8a77990-cpg-mssr.c | 18 +++++++++---------
>  4 files changed, 35 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> index e5fa9f6c1ec4b9cb..9e9a6f2c31e808eb 100644
> --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> @@ -3,7 +3,7 @@
>   * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
>   *
>   * Copyright (C) 2015 Glider bvba
> - * Copyright (C) 2018 Renesas Electronics Corp.
> + * Copyright (C) 2018-2019 Renesas Electronics Corp.
>   *
>   * Based on clk-rcar-gen3.c
>   *
> @@ -156,14 +156,14 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
>  	DEF_MOD("intc-ap",		 408,	R8A7795_CLK_S0D3),
>  	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S1D2),
>  	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S1D2),
> -	DEF_MOD("drif7",		 508,	R8A7795_CLK_S3D2),
> -	DEF_MOD("drif6",		 509,	R8A7795_CLK_S3D2),
> -	DEF_MOD("drif5",		 510,	R8A7795_CLK_S3D2),
> -	DEF_MOD("drif4",		 511,	R8A7795_CLK_S3D2),
> -	DEF_MOD("drif3",		 512,	R8A7795_CLK_S3D2),
> -	DEF_MOD("drif2",		 513,	R8A7795_CLK_S3D2),
> -	DEF_MOD("drif1",		 514,	R8A7795_CLK_S3D2),
> -	DEF_MOD("drif0",		 515,	R8A7795_CLK_S3D2),
> +	DEF_MOD("drif31",		 508,	R8A7795_CLK_S3D2),
> +	DEF_MOD("drif30",		 509,	R8A7795_CLK_S3D2),
> +	DEF_MOD("drif21",		 510,	R8A7795_CLK_S3D2),
> +	DEF_MOD("drif20",		 511,	R8A7795_CLK_S3D2),
> +	DEF_MOD("drif11",		 512,	R8A7795_CLK_S3D2),
> +	DEF_MOD("drif10",		 513,	R8A7795_CLK_S3D2),
> +	DEF_MOD("drif01",		 514,	R8A7795_CLK_S3D2),
> +	DEF_MOD("drif00",		 515,	R8A7795_CLK_S3D2),
>  	DEF_MOD("hscif4",		 516,	R8A7795_CLK_S3D1),
>  	DEF_MOD("hscif3",		 517,	R8A7795_CLK_S3D1),
>  	DEF_MOD("hscif2",		 518,	R8A7795_CLK_S3D1),
> diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> index 73c69152c77b02ed..d8e9af5d9ae9cf6e 100644
> --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> @@ -149,14 +149,14 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
>  	DEF_MOD("intc-ap",		 408,	R8A7796_CLK_S0D3),
>  	DEF_MOD("audmac1",		 501,	R8A7796_CLK_S1D2),
>  	DEF_MOD("audmac0",		 502,	R8A7796_CLK_S1D2),
> -	DEF_MOD("drif7",		 508,	R8A7796_CLK_S3D2),
> -	DEF_MOD("drif6",		 509,	R8A7796_CLK_S3D2),
> -	DEF_MOD("drif5",		 510,	R8A7796_CLK_S3D2),
> -	DEF_MOD("drif4",		 511,	R8A7796_CLK_S3D2),
> -	DEF_MOD("drif3",		 512,	R8A7796_CLK_S3D2),
> -	DEF_MOD("drif2",		 513,	R8A7796_CLK_S3D2),
> -	DEF_MOD("drif1",		 514,	R8A7796_CLK_S3D2),
> -	DEF_MOD("drif0",		 515,	R8A7796_CLK_S3D2),
> +	DEF_MOD("drif31",		 508,	R8A7796_CLK_S3D2),
> +	DEF_MOD("drif30",		 509,	R8A7796_CLK_S3D2),
> +	DEF_MOD("drif21",		 510,	R8A7796_CLK_S3D2),
> +	DEF_MOD("drif20",		 511,	R8A7796_CLK_S3D2),
> +	DEF_MOD("drif11",		 512,	R8A7796_CLK_S3D2),
> +	DEF_MOD("drif10",		 513,	R8A7796_CLK_S3D2),
> +	DEF_MOD("drif01",		 514,	R8A7796_CLK_S3D2),
> +	DEF_MOD("drif00",		 515,	R8A7796_CLK_S3D2),
>  	DEF_MOD("hscif4",		 516,	R8A7796_CLK_S3D1),
>  	DEF_MOD("hscif3",		 517,	R8A7796_CLK_S3D1),
>  	DEF_MOD("hscif2",		 518,	R8A7796_CLK_S3D1),
> diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> index a0ce2ecb656d3d48..8f87e314d9490498 100644
> --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> @@ -3,6 +3,7 @@
>   * r8a77965 Clock Pulse Generator / Module Standby and Software Reset
>   *
>   * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
> + * Copyright (C) 2019 Renesas Electronics Corp.
>   *
>   * Based on r8a7795-cpg-mssr.c
>   *
> @@ -148,14 +149,14 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
>  
>  	DEF_MOD("audmac1",		501,	R8A77965_CLK_S1D2),
>  	DEF_MOD("audmac0",		502,	R8A77965_CLK_S1D2),
> -	DEF_MOD("drif7",		508,	R8A77965_CLK_S3D2),
> -	DEF_MOD("drif6",		509,	R8A77965_CLK_S3D2),
> -	DEF_MOD("drif5",		510,	R8A77965_CLK_S3D2),
> -	DEF_MOD("drif4",		511,	R8A77965_CLK_S3D2),
> -	DEF_MOD("drif3",		512,	R8A77965_CLK_S3D2),
> -	DEF_MOD("drif2",		513,	R8A77965_CLK_S3D2),
> -	DEF_MOD("drif1",		514,	R8A77965_CLK_S3D2),
> -	DEF_MOD("drif0",		515,	R8A77965_CLK_S3D2),
> +	DEF_MOD("drif31",		508,	R8A77965_CLK_S3D2),
> +	DEF_MOD("drif30",		509,	R8A77965_CLK_S3D2),
> +	DEF_MOD("drif21",		510,	R8A77965_CLK_S3D2),
> +	DEF_MOD("drif20",		511,	R8A77965_CLK_S3D2),
> +	DEF_MOD("drif11",		512,	R8A77965_CLK_S3D2),
> +	DEF_MOD("drif10",		513,	R8A77965_CLK_S3D2),
> +	DEF_MOD("drif01",		514,	R8A77965_CLK_S3D2),
> +	DEF_MOD("drif00",		515,	R8A77965_CLK_S3D2),
>  	DEF_MOD("hscif4",		516,	R8A77965_CLK_S3D1),
>  	DEF_MOD("hscif3",		517,	R8A77965_CLK_S3D1),
>  	DEF_MOD("hscif2",		518,	R8A77965_CLK_S3D1),
> diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> index 53973201a9f576ad..9570404baa583a8f 100644
> --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> @@ -2,7 +2,7 @@
>  /*
>   * r8a77990 Clock Pulse Generator / Module Standby and Software Reset
>   *
> - * Copyright (C) 2018 Renesas Electronics Corp.
> + * Copyright (C) 2018-2019 Renesas Electronics Corp.
>   *
>   * Based on r8a7795-cpg-mssr.c
>   *
> @@ -154,14 +154,14 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
>  	DEF_MOD("intc-ap",		 408,	R8A77990_CLK_S0D3),
>  
>  	DEF_MOD("audmac0",		 502,	R8A77990_CLK_S1D2),
> -	DEF_MOD("drif7",		 508,	R8A77990_CLK_S3D2),
> -	DEF_MOD("drif6",		 509,	R8A77990_CLK_S3D2),
> -	DEF_MOD("drif5",		 510,	R8A77990_CLK_S3D2),
> -	DEF_MOD("drif4",		 511,	R8A77990_CLK_S3D2),
> -	DEF_MOD("drif3",		 512,	R8A77990_CLK_S3D2),
> -	DEF_MOD("drif2",		 513,	R8A77990_CLK_S3D2),
> -	DEF_MOD("drif1",		 514,	R8A77990_CLK_S3D2),
> -	DEF_MOD("drif0",		 515,	R8A77990_CLK_S3D2),
> +	DEF_MOD("drif31",		 508,	R8A77990_CLK_S3D2),
> +	DEF_MOD("drif30",		 509,	R8A77990_CLK_S3D2),
> +	DEF_MOD("drif21",		 510,	R8A77990_CLK_S3D2),
> +	DEF_MOD("drif20",		 511,	R8A77990_CLK_S3D2),
> +	DEF_MOD("drif11",		 512,	R8A77990_CLK_S3D2),
> +	DEF_MOD("drif10",		 513,	R8A77990_CLK_S3D2),
> +	DEF_MOD("drif01",		 514,	R8A77990_CLK_S3D2),
> +	DEF_MOD("drif00",		 515,	R8A77990_CLK_S3D2),
>  	DEF_MOD("hscif4",		 516,	R8A77990_CLK_S3D1C),
>  	DEF_MOD("hscif3",		 517,	R8A77990_CLK_S3D1C),
>  	DEF_MOD("hscif2",		 518,	R8A77990_CLK_S3D1C),
> -- 
> 2.17.1
> 

      reply	other threads:[~2019-03-29  9:39 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-27 12:41 [PATCH 0/5] clk: renesas: rcar-gen3: Errata Updates Geert Uytterhoeven
2019-03-27 12:41 ` [PATCH 1/5] clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI Geert Uytterhoeven
2019-03-29  9:02   ` Simon Horman
2019-03-29  9:07     ` Geert Uytterhoeven
2019-03-29  9:19       ` Simon Horman
2019-03-27 12:41 ` [PATCH 2/5] clk: renesas: rcar-gen3: Correct parent clock of HS-USB Geert Uytterhoeven
2019-03-29  9:20   ` Simon Horman
2019-03-27 12:41 ` [PATCH 3/5] clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC Geert Uytterhoeven
2019-03-29  9:32   ` Simon Horman
2019-03-27 12:41 ` [PATCH 4/5] clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC Geert Uytterhoeven
2019-03-29  9:34   ` Simon Horman
2019-03-27 12:41 ` [PATCH 5/5] clk: renesas: rcar-gen3: Rename DRIF clocks Geert Uytterhoeven
2019-03-29  9:39   ` Simon Horman [this message]

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