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[89.233.230.99]) by smtp.gmail.com with ESMTPSA id d2sm3183876ljc.84.2019.06.03.09.23.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Jun 2019 09:23:27 -0700 (PDT) Date: Mon, 3 Jun 2019 18:23:26 +0200 From: Niklas =?iso-8859-1?Q?S=F6derlund?= To: Yoshihiro Shimoda Cc: wim@linux-watchdog.org, linux@roeck-us.net, linux-watchdog@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v2] watchdog: renesas_wdt: Add a few cycles delay Message-ID: <20190603162326.GB2960@bigcity.dyn.berto.se> References: <1559558161-31244-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1559558161-31244-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> User-Agent: Mutt/1.11.4 (2019-03-13) Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hi Shimoda-san, Thanks for your work. On 2019-06-03 19:36:01 +0900, Yoshihiro Shimoda wrote: > According to the hardware manual of R-Car Gen2 and Gen3, > software should wait a few RLCK cycles as following: > - Delay 2 cycles before setting watchdog counter. > - Delay 3 cycles before disabling module clock. > > So, this patch adds such delays. > > Signed-off-by: Yoshihiro Shimoda > Reviewed-by: Geert Uytterhoeven Small nit bellow, with or without that addressed. Reviewed-by: Niklas Söderlund > --- > Changes from v1 (https://patchwork.kernel.org/patch/10972641/): > - Change formula to improve accuracy. > - Add Geert-san's Reviewed-by. > > drivers/watchdog/renesas_wdt.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c > index 565dbc1..525a1fe 100644 > --- a/drivers/watchdog/renesas_wdt.c > +++ b/drivers/watchdog/renesas_wdt.c > @@ -7,6 +7,7 @@ > */ > #include > #include > +#include > #include > #include > #include > @@ -70,6 +71,15 @@ static int rwdt_init_timeout(struct watchdog_device *wdev) > return 0; > } > > +static void rwdt_wait(struct rwdt_priv *priv, unsigned int cycles) > +{ > + unsigned long delays; Could this be unsigned int? It would still fit for a cycles number around 2000 and this change use 2 and 3 cycles. > + > + delays = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate); > + > + usleep_range(delays, 2 * delays); > +} > + > static int rwdt_start(struct watchdog_device *wdev) > { > struct rwdt_priv *priv = watchdog_get_drvdata(wdev); > @@ -80,6 +90,8 @@ static int rwdt_start(struct watchdog_device *wdev) > /* Stop the timer before we modify any register */ > val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME; > rwdt_write(priv, val, RWTCSRA); > + /* Delay 2 cycles before setting watchdog counter */ > + rwdt_wait(priv, 2); > > rwdt_init_timeout(wdev); > rwdt_write(priv, priv->cks, RWTCSRA); > @@ -98,6 +110,8 @@ static int rwdt_stop(struct watchdog_device *wdev) > struct rwdt_priv *priv = watchdog_get_drvdata(wdev); > > rwdt_write(priv, priv->cks, RWTCSRA); > + /* Delay 3 cycles before disabling module clock */ > + rwdt_wait(priv, 3); > pm_runtime_put(wdev->parent); > > return 0; > -- > 2.7.4 > -- Regards, Niklas Söderlund