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[217.31.177.236]) by smtp.gmail.com with ESMTPSA id h5sm650021ljf.83.2019.08.30.15.06.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2019 15:06:36 -0700 (PDT) Date: Sat, 31 Aug 2019 00:06:36 +0200 From: Niklas =?iso-8859-1?Q?S=F6derlund?= To: Geert Uytterhoeven Cc: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v2 3/8] clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate() Message-ID: <20190830220636.GS8479@bigcity.dyn.berto.se> References: <20190830134515.11925-1-geert+renesas@glider.be> <20190830134515.11925-4-geert+renesas@glider.be> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20190830134515.11925-4-geert+renesas@glider.be> User-Agent: Mutt/1.12.1 (2019-06-15) Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hi Geert, Thanks for your patch. On 2019-08-30 15:45:10 +0200, Geert Uytterhoeven wrote: > The .set_rate() callback for the SD clocks is always called with a valid > clock rate, returned by .round_rate(). Hence there is no need to > iterate through the divider table twice: once to repeat the work done by > .round_rate(), and a second time to find the corresponding divider > entry. > > Just iterate once, looking for the divider that matches the passed clock > rate. > > Signed-off-by: Geert Uytterhoeven Clever :-) Reviewed-by: Niklas Söderlund > --- > v2: > - No changes. > --- > drivers/clk/renesas/rcar-gen3-cpg.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c > index 3480284a08308134..9f457411984b1ca4 100644 > --- a/drivers/clk/renesas/rcar-gen3-cpg.c > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c > @@ -339,14 +339,14 @@ static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, > } > > static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, > - unsigned long parent_rate) > + unsigned long parent_rate) > { > struct sd_clock *clock = to_sd_clock(hw); > - unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); > unsigned int i; > > for (i = 0; i < clock->div_num; i++) > - if (div == clock->div_table[i].div) > + if (rate == DIV_ROUND_CLOSEST(parent_rate, > + clock->div_table[i].div)) > break; > > if (i >= clock->div_num) > -- > 2.17.1 > -- Regards, Niklas Söderlund