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From: Ulrich Hecht <uli+renesas@fpond.eu>
To: linux-renesas-soc@vger.kernel.org
Cc: wsa@the-dreams.de, geert@linux-m68k.org, hoai.luu.ub@renesas.com,
	Ulrich Hecht <uli+renesas@fpond.eu>
Subject: [PATCH v3 0/6] pinctrl: renesas: basic R8A779A0 (V3U) support
Date: Tue, 12 Jan 2021 17:59:06 +0100
Message-ID: <20210112165912.30876-1-uli+renesas@fpond.eu> (raw)

Hi!

This series provides basic V3U pin control support, up to and including the
SCIF pins.

This revision includes yet more fixes for issues found by Geert in his
review. It also adds DT bindings and Reviewed-by/Tested-by tags where
appropriate; see below for details.

Thanks to Geert and Wolfram for review and testing!

CU
Uli


Changes since v2:
- pinctrl.c: fix signedness of lower_voltage
- use SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 where applicable
- sh_pfc.h: use PORT_GP_CFG_2 where appropriate
- sh_pfc.h: document changed unlock_reg behavior
- pfc-r8a779a0.c: fix table alignment issues
- pfc-r8a779a0.c: fix imprecise pin names in comments
- pfc-r8a779a0.c: remove redundant initializations
- add DT bindings (DT node sold separately)
- add Reviewed-by/Tested-by tags where applicable

Changes since v1:
- add support for different voltage levels
- add more PORT_GP_CFG_{2,31} macros
- add non-GP pins
- add A/B pins/groups for TCLK{1,2}, {RX,TX}1, FXR_TXDA, RXDA_EXTFXR
- add SEL_I2C*_0 to MOD_SEL2
- add PINMUX_PHYS, fix multiplexing of S{DA,CL}[0-6]
- add AVB{0,1}_{MAGIC,MDC,MDIO,TXREFCLK}
- remove undocumented POC3
- add human-readable pin names to pinmux_bias_regs[]
- use generic rcar_pinmux_{get,set}_bias() ops
- tweak coding style and commit messages
- add Reviewed-Bys where applicable

Ulrich Hecht (6):
  pinctrl: renesas: implement unlock register masks
  pinctrl: renesas: add I/O voltage level flag
  pinctrl: renesas: add PORT_GP_CFG_{2,31} macros
  pinctrl: renesas: Initial R8A779A0 (V3U) PFC support
  pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functions
  dt-bindings: pinctrl: sh-pfc: Document r8a779a0 PFC support

 .../bindings/pinctrl/renesas,pfc.yaml         |    1 +
 drivers/pinctrl/renesas/Kconfig               |    5 +
 drivers/pinctrl/renesas/Makefile              |    1 +
 drivers/pinctrl/renesas/core.c                |   34 +-
 drivers/pinctrl/renesas/pfc-r8a779a0.c        | 2672 +++++++++++++++++
 drivers/pinctrl/renesas/pinctrl.c             |   16 +-
 drivers/pinctrl/renesas/sh_pfc.h              |   28 +-
 7 files changed, 2740 insertions(+), 17 deletions(-)
 create mode 100644 drivers/pinctrl/renesas/pfc-r8a779a0.c

-- 
2.20.1


             reply index

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-12 16:59 Ulrich Hecht [this message]
2021-01-12 16:59 ` [PATCH v3 1/6] pinctrl: renesas: implement unlock register masks Ulrich Hecht
2021-01-13 13:25   ` Geert Uytterhoeven
2021-01-12 16:59 ` [PATCH v3 2/6] pinctrl: renesas: add I/O voltage level flag Ulrich Hecht
2021-01-13 13:29   ` Geert Uytterhoeven
2021-01-12 16:59 ` [PATCH v3 3/6] pinctrl: renesas: add PORT_GP_CFG_{2,31} macros Ulrich Hecht
2021-01-13 13:32   ` Geert Uytterhoeven
2021-01-12 16:59 ` [PATCH v3 5/6] pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functions Ulrich Hecht
2021-01-12 16:59 ` [PATCH v3 6/6] dt-bindings: pinctrl: sh-pfc: Document r8a779a0 PFC support Ulrich Hecht
2021-01-13 13:43   ` Geert Uytterhoeven
     [not found] ` <20210112165912.30876-5-uli+renesas@fpond.eu>
2021-01-13 13:37   ` [PATCH v3 4/6] pinctrl: renesas: Initial R8A779A0 (V3U) " Geert Uytterhoeven

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