From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v3 02/10] drivers: clk: renesas: r9a07g044-cpg: Rename divider table
Date: Fri, 25 Jun 2021 20:54:47 +0100 [thread overview]
Message-ID: <20210625195455.3607-3-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20210625195455.3607-1-biju.das.jz@bp.renesas.com>
As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV
and CPG_PL2_DDIV(for P0) shares same divider table entries. Rename
clk_div_table dtable_3b to clk_div_table dtable_1_32 so that it
can be reused.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2->v3
* Channged the divider table name to dtable_1_32.
* Added Geert's Rb tag
v2:
* New patch
---
drivers/clk/renesas/r9a07g044-cpg.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 50b5269586a4..d5803fb1242e 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -42,12 +42,13 @@ enum clk_ids {
};
/* Divider tables */
-static const struct clk_div_table dtable_3b[] = {
+static const struct clk_div_table dtable_1_32[] = {
{0, 1},
{1, 2},
{2, 4},
{3, 8},
{4, 32},
+ {0, 0},
};
static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
@@ -72,10 +73,10 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
/* Core output clk */
DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
- dtable_3b, CLK_DIVIDER_HIWORD_MASK),
+ dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
- DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK),
+ DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
};
static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
--
2.17.1
next prev parent reply other threads:[~2021-06-25 19:55 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-25 19:54 [PATCH v3 00/10] Update clock definitions Biju Das
2021-06-25 19:54 ` [PATCH v3 01/10] drivers: clk: renesas: renesas-rzg2l-cpg: Add multi clock PM support Biju Das
2021-06-25 19:54 ` Biju Das [this message]
2021-06-25 19:54 ` [PATCH v3 03/10] drivers: clk: renesas: r9a07g044-cpg: Fix P1 Clock Biju Das
2021-06-25 19:54 ` [PATCH v3 04/10] drivers: clk: renesas: r9a07g044-cpg: Add P2 Clock support Biju Das
2021-06-25 19:54 ` [PATCH v3 05/10] dt-bindings: clk: r9a07g044-cpg: Update clock/reset definitions Biju Das
2021-06-25 19:54 ` [PATCH v3 06/10] drivers: clk: renesas: r9a07g044-cpg: Update {GIC,IA55,SCIF} clock/reset entries Biju Das
2021-06-25 19:54 ` [PATCH v3 07/10] arm64: dts: renesas: r9a07g044: Update SCIF0 clock/reset Biju Das
2021-06-25 19:54 ` [PATCH v3 08/10] drivers: clk: renesas: r9a07g044-cpg: Add I2C clocks/resets Biju Das
2021-06-25 19:54 ` [PATCH v3 09/10] drivers: clk: renesas: r9a07g044-cpg: Add DMAC clocks/resets Biju Das
2021-06-25 19:54 ` [PATCH v3 10/10] arm64: dts: renesas: r9a07g044: Add I2C nodes Biju Das
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