From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDF09C48BC2 for ; Fri, 25 Jun 2021 19:55:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DA2B861445 for ; Fri, 25 Jun 2021 19:55:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229853AbhFYT5k (ORCPT ); Fri, 25 Jun 2021 15:57:40 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:8739 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229741AbhFYT5j (ORCPT ); Fri, 25 Jun 2021 15:57:39 -0400 X-IronPort-AV: E=Sophos;i="5.83,299,1616425200"; d="scan'208";a="85449075" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 26 Jun 2021 04:55:18 +0900 Received: from localhost.localdomain (unknown [10.226.92.12]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 6B91340E6204; Sat, 26 Jun 2021 04:55:16 +0900 (JST) From: Biju Das To: Rob Herring Cc: Biju Das , Lad Prabhakar , devicetree@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 07/10] arm64: dts: renesas: r9a07g044: Update SCIF0 clock/reset Date: Fri, 25 Jun 2021 20:54:52 +0100 Message-Id: <20210625195455.3607-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210625195455.3607-1-biju.das.jz@bp.renesas.com> References: <20210625195455.3607-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Update SCIF0 clock and reset index in SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v2->v3: * Added Geert's Rb tag. v1->v2: * Updated reset entries --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 734c8adeceba..01482d227506 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -82,10 +82,10 @@ ; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>; + clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; clock-names = "fck"; power-domains = <&cpg>; - resets = <&cpg R9A07G044_CLK_SCIF0>; + resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>; status = "disabled"; }; -- 2.17.1