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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 2/9] drivers: clk: renesas: r9a07g044-cpg: Add SSIF-2 clock and reset entries
Date: Fri,  2 Jul 2021 14:50:03 +0100	[thread overview]
Message-ID: <20210702135010.5937-3-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20210702135010.5937-1-biju.das.jz@bp.renesas.com>

Add SSIF-2 clock and reset entries in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g044-cpg.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 7af4b39a0953..ed5f5c11ac12 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -96,6 +96,22 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
 				0x52c, 0),
 	DEF_MOD("dmac_pclk",	R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
 				0x52c, 1),
+	DEF_MOD("ssi0_pclk",	R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
+				0x570, 0),
+	DEF_MOD("ssi0_sfr",	R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
+				0x570, 1),
+	DEF_MOD("ssi1_pclk",	R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
+				0x570, 2),
+	DEF_MOD("ssi1_sfr",	R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
+				0x570, 3),
+	DEF_MOD("ssi2_pclk",	R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
+				0x570, 4),
+	DEF_MOD("ssi2_sfr",	R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
+				0x570, 5),
+	DEF_MOD("ssi3_pclk",	R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
+				0x570, 6),
+	DEF_MOD("ssi3_sfr",	R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
+				0x570, 7),
 	DEF_MOD("usb0_host",	R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
 				0x578, 0),
 	DEF_MOD("usb1_host",	R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
@@ -132,6 +148,10 @@ static struct rzg2l_reset r9a07g044_resets[] = {
 	DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
 	DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
 	DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
+	DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
+	DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
+	DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
+	DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
 	DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
 	DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
 	DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
-- 
2.17.1


  parent reply	other threads:[~2021-07-02 13:50 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-02 13:50 [PATCH 0/9] Add RZ/G2L Sound support Biju Das
2021-07-02 13:50 ` [PATCH 1/9] ASoC: dt-bindings: Document RZ/G2L bindings Biju Das
2021-07-02 21:23   ` Rob Herring
2021-07-19 13:43     ` Biju Das
2021-07-02 13:50 ` Biju Das [this message]
2021-07-02 14:03   ` [PATCH 2/9] drivers: clk: renesas: r9a07g044-cpg: Add SSIF-2 clock and reset entries Geert Uytterhoeven
2021-07-02 13:50 ` [PATCH 3/9] sound: soc: sh: Add RZ/G2L SSIF-2 driver Biju Das
2021-07-02 13:50 ` [PATCH 4/9] arm64: dts: renesas: r9a07g044: Add external audio clock nodes Biju Das
2021-07-02 13:50 ` [PATCH 5/9] arm64: dts: renesas: r9a07g044: Add SSI support Biju Das
2021-07-02 13:50 ` [PATCH 6/9] arm64: defconfig: Enable ASoC sound support for RZ/G2L SoC Biju Das
2021-07-02 13:50 ` [PATCH 7/9] ASoC: dt-bindings: sound: renesas,rz-ssi: Document DMA support Biju Das
2021-07-02 13:50 ` [PATCH 8/9] sound: sh: rz-ssi: Add SSI DMAC support Biju Das
2021-07-02 13:50 ` [PATCH 9/9] arm64: dts: renesas: r9a07g044: Add SSI DMA support Biju Das

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