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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH net-next 03/18] drivers: clk: renesas: r9a07g044-cpg: Add ethernet clock sources
Date: Thu, 22 Jul 2021 15:13:36 +0100	[thread overview]
Message-ID: <20210722141351.13668-4-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20210722141351.13668-1-biju.das.jz@bp.renesas.com>

Ethernet reference clock can be sourced from PLL5_2 or PLL6_2. Add support
for ethernet source clock selection using SEL_PLL_6_2 mux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g044-cpg.c | 17 +++++++++++++++++
 drivers/clk/renesas/rzg2l-cpg.h     |  6 ++++++
 2 files changed, 23 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 9e9e8fb6d00d..c78bea2f6ea8 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -35,8 +35,10 @@ enum clk_ids {
 	CLK_PLL3_DIV4,
 	CLK_PLL4,
 	CLK_PLL5,
+	CLK_PLL5_2,
 	CLK_PLL5_DIV2,
 	CLK_PLL6,
+	CLK_PLL6_DIV2,
 	CLK_P1_DIV2,
 
 	/* Module Clocks */
@@ -53,6 +55,9 @@ static const struct clk_div_table dtable_1_32[] = {
 	{0, 0},
 };
 
+/* Mux clock tables */
+static const char * const sel_pll6_2[]	= { ".pll6_2_div2", ".pll5_2_div2" };
+
 static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
 	/* External Clock Inputs */
 	DEF_INPUT("extal", CLK_EXTAL),
@@ -64,6 +69,11 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
 	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
 	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
 
+	DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
+	DEF_FIXED(".pll5_2", CLK_PLL5_2, CLK_PLL5, 1, 6),
+
+	DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
+
 	DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
 	DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
 	DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
@@ -73,6 +83,9 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
 	DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
 	DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
 
+	DEF_FIXED(".pll5_2_div2", CLK_PLL5_DIV2, CLK_PLL5_2, 1, 2),
+	DEF_FIXED(".pll6_2_div2", CLK_PLL6_DIV2, CLK_PLL6, 1, 2),
+
 	/* Core output clk */
 	DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
 	DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
@@ -83,6 +96,10 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
 	DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
 	DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
 		DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+	DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
+	DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
+	DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,
+		sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
 };
 
 static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 148db5de253b..5202c0512483 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -11,6 +11,7 @@
 
 #define CPG_PL2_DDIV		(0x204)
 #define CPG_PL3A_DDIV		(0x208)
+#define CPG_PL6_ETH_SSEL	(0x418)
 
 /* n = 0/1/2 for PLL1/4/6 */
 #define CPG_SAMPLL_CLK1(n)	(0x04 + (16 * n))
@@ -24,6 +25,11 @@
 #define DIVPL3A		DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
 #define DIVPL3B		DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
 
+#define SEL_PLL_PACK(offset, bitpos, size) \
+		(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
+
+#define SEL_PLL6_2	SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)
+
 /**
  * Definitions of CPG Core Clocks
  *
-- 
2.17.1


  parent reply	other threads:[~2021-07-22 14:14 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-22 14:13 [PATCH net-next 00/18] Add Gigabit Ethernet driver support Biju Das
2021-07-22 14:13 ` [PATCH net-next 01/18] dt-bindings: net: renesas,etheravb: Document Gigabit Ethernet IP Biju Das
2021-07-22 14:13 ` [PATCH net-next 02/18] drivers: clk: renesas: rzg2l-cpg: Add support to handle MUX clocks Biju Das
2021-07-23 10:26   ` Sergei Shtylyov
2021-07-23 12:12     ` Biju Das
2021-07-26 10:53   ` Geert Uytterhoeven
2021-07-26 12:23     ` Biju Das
2021-07-22 14:13 ` Biju Das [this message]
2021-07-26 10:50   ` [PATCH net-next 03/18] drivers: clk: renesas: r9a07g044-cpg: Add ethernet clock sources Geert Uytterhoeven
2021-07-26 11:43     ` Biju Das
2021-07-26 11:50       ` Geert Uytterhoeven
2021-07-22 14:13 ` [PATCH net-next 04/18] drivers: clk: renesas: r9a07g044-cpg: Add GbEthernet clock/reset Biju Das
2021-07-26 10:11   ` Geert Uytterhoeven
2021-07-26 10:18     ` Biju Das
2021-07-22 14:13 ` [PATCH net-next 05/18] ravb: Replace chip type with a structure for driver data Biju Das
2021-07-22 20:42   ` Sergei Shtylyov
2021-07-23  6:08     ` Biju Das
2021-07-22 14:13 ` [PATCH net-next 06/18] ravb: Factorise ptp feature Biju Das
2021-07-23 20:56   ` Sergei Shtylyov
2021-07-26  9:01     ` Biju Das
2021-07-26 13:08       ` Andrew Lunn
2021-07-26 13:41         ` Biju Das
2021-07-22 14:13 ` [PATCH net-next 07/18] ravb: Add features specific to R-Car Gen3 Biju Das
2021-07-22 14:13 ` [PATCH net-next 08/18] ravb: Add R-Car common features Biju Das
2021-07-27 20:48   ` Sergei Shtylyov
2021-07-28 10:13     ` Biju Das
2021-07-28 13:45       ` Andrew Lunn
2021-07-29 15:10         ` Biju Das
2021-07-22 14:13 ` [PATCH net-next 09/18] ravb: Factorise ravb_ring_free function Biju Das
2021-07-29 18:02   ` Sergei Shtylyov
2021-07-30  6:21     ` Biju Das
2021-08-20 15:32       ` Biju Das
2021-07-22 14:13 ` [PATCH net-next 10/18] ravb: Factorise ravb_ring_format function Biju Das
2021-07-29 18:30   ` Sergei Shtylyov
2021-07-30  6:24     ` Biju Das
2021-07-22 14:13 ` [PATCH net-next 11/18] ravb: Factorise ravb_ring_init function Biju Das
2021-07-29 18:53   ` Sergei Shtylyov
2021-07-30  6:54     ` Biju Das
2021-07-22 14:13 ` [PATCH net-next 12/18] ravb: Factorise {emac,dmac} init function Biju Das
2021-08-02 19:41   ` Sergei Shtylyov
2021-08-20 15:42     ` Biju Das
2021-08-20 18:57       ` Sergey Shtylyov
2021-08-20 19:44         ` Biju Das
2021-07-22 14:13 ` [PATCH net-next 13/18] ravb: Factorise ravb_rx function Biju Das
2021-07-22 14:13 ` [PATCH net-next 14/18] ravb: Factorise ravb_adjust_link function Biju Das
2021-07-22 14:13 ` [PATCH net-next 15/18] ravb: Factorise ravb_set_features Biju Das
2021-07-22 14:13 ` [PATCH net-next 16/18] ravb: Add reset support Biju Das
2021-07-22 14:13 ` [PATCH net-next 17/18] ravb: Add GbEthernet driver support Biju Das
2021-07-22 14:13 ` [PATCH net-next 18/18] arm64: dts: renesas: r9a07g044: Add GbEther nodes Biju Das
2021-07-22 20:53 ` [PATCH net-next 00/18] Add Gigabit Ethernet driver support Sergei Shtylyov
2021-07-22 21:07   ` Andrew Lunn
2021-07-23  6:28     ` Biju Das
2021-07-26 10:55       ` Geert Uytterhoeven
2021-07-26 13:49         ` Arnd Bergmann
2021-07-23  6:23   ` Biju Das

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