[PATCH 0/2] Add SDHI clock and reset entries in cpg driver

[Biju Das <biju.das.jz@bp.renesas.com>]

Add SDHI clock and reset entries in cpg driver.

As per the HW manual, we should not directly switch from 533 MHz
to 400 MHz and vice versa. To change the setting from 533 MHz to 400 MHz
or vice versa, Switch to 266 MHz first,and then switch to the target
setting 533 MHz or 400 MHz. So added support in mux to handle this
condition.

This patch series is based on renesas-clk-for-v5.15 [1] 
[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/?h=renesas-clk-for-v5.15

This patch series depend upon [2]
[2] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=522063

Biju Das (2):
  drivers: clk: renesas: rzg2l-cpg: Add SDHI clk mux support
  drivers: clk: renesas: r9a07g044-cpg: Add SDHI clock and reset entries

 drivers/clk/renesas/r9a07g044-cpg.c |  37 ++++++++++
 drivers/clk/renesas/rzg2l-cpg.c     | 106 ++++++++++++++++++++++++++++
 drivers/clk/renesas/rzg2l-cpg.h     |  12 ++++
 3 files changed, 155 insertions(+)

-- 
2.17.1