From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B2C2C433F5 for ; Fri, 24 Sep 2021 10:23:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3CF43610CB for ; Fri, 24 Sep 2021 10:23:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238724AbhIXKZT (ORCPT ); Fri, 24 Sep 2021 06:25:19 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:4596 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229911AbhIXKZT (ORCPT ); Fri, 24 Sep 2021 06:25:19 -0400 X-IronPort-AV: E=Sophos;i="5.85,319,1624287600"; d="scan'208";a="94920609" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 24 Sep 2021 19:23:44 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id D21AF401070E; Fri, 24 Sep 2021 19:23:42 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2] arm64: dts: renesas: rzg2l-smarc: Enable CANFD Date: Fri, 24 Sep 2021 11:23:38 +0100 Message-Id: <20210924102338.11595-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Enable CANFD on RZ/G2L SMARC platform. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2: -> Corrected STB pin states --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 40 ++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index e895f6e7fa28..a02784fab46a 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -80,6 +80,20 @@ clock-frequency = <12288000>; }; +&canfd { + pinctrl-0 = <&can0_pins &can1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; + + channel1 { + status = "okay"; + }; +}; + &ehci0 { dr_mode = "otg"; status = "okay"; @@ -139,6 +153,32 @@ pinctrl-0 = <&sound_clk_pins>; pinctrl-names = "default"; + can0_pins: can0 { + pinmux = , /* TX */ + ; /* RX */ + }; + + /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */ + can0-stb { + gpio-hog; + gpios = ; + output-low; + line-name = "can0_stb"; + }; + + can1_pins: can1 { + pinmux = , /* TX */ + ; /* RX */ + }; + + /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ + can1-stb { + gpio-hog; + gpios = ; + output-low; + line-name = "can1_stb"; + }; + i2c0_pins: i2c0 { pins = "RIIC0_SDA", "RIIC0_SCL"; input-enable; -- 2.17.1