From: Bjorn Helgaas <helgaas@kernel.org>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be,
magnus.damm@gmail.com, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v5 03/12] PCI: Add PCI_EXP_LNKCAP_MLW macros
Date: Tue, 20 Sep 2022 15:08:23 -0500 [thread overview]
Message-ID: <20220920200823.GA1134038@bhelgaas> (raw)
In-Reply-To: <20220905071257.1059436-4-yoshihiro.shimoda.uh@renesas.com>
On Mon, Sep 05, 2022 at 04:12:48PM +0900, Yoshihiro Shimoda wrote:
> Add macros defining Maximum Link Width bits in Link Capabilities
> Register.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
> include/uapi/linux/pci_regs.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 57b8e2ffb1dd..c9f4c452e210 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -538,6 +538,13 @@
> #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
> #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
> #define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */
> +#define PCI_EXP_LNKCAP_MLW_X1 0x00000010 /* Maximum Link Width x1 */
> +#define PCI_EXP_LNKCAP_MLW_X2 0x00000020 /* Maximum Link Width x2 */
> +#define PCI_EXP_LNKCAP_MLW_X4 0x00000040 /* Maximum Link Width x4 */
> +#define PCI_EXP_LNKCAP_MLW_X8 0x00000080 /* Maximum Link Width x8 */
> +#define PCI_EXP_LNKCAP_MLW_X12 0x000000c0 /* Maximum Link Width x12 */
> +#define PCI_EXP_LNKCAP_MLW_X16 0x00000100 /* Maximum Link Width x16 */
> +#define PCI_EXP_LNKCAP_MLW_X32 0x00000200 /* Maximum Link Width x32 */
In PCIe r6.0, x32 is mentioned a few times, but not actually defined
for Link Capabilities. Has it been defined in an ECN or something?
Bjorn
next prev parent reply other threads:[~2022-09-20 20:08 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-05 7:12 [PATCH v5 00/12] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 01/12] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 02/12] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 03/12] PCI: Add PCI_EXP_LNKCAP_MLW macros Yoshihiro Shimoda
2022-09-20 20:08 ` Bjorn Helgaas [this message]
2022-09-21 0:05 ` Yoshihiro Shimoda
2022-09-21 2:22 ` Bjorn Helgaas
2022-09-21 8:50 ` Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 04/12] PCI: controller: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2022-09-20 20:00 ` Bjorn Helgaas
2022-09-05 7:12 ` [PATCH v5 05/12] PCI: dwc: Add ep_pre_init() callback to dw_pcie_ep_ops Yoshihiro Shimoda
2022-09-20 20:03 ` Bjorn Helgaas
2022-09-05 7:12 ` [PATCH v5 06/12] PCI: dwc: Add reset_all_bars flag Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 07/12] PCI: dwc: Avoid reading a register to detect whether eDMA exists Yoshihiro Shimoda
2022-09-05 8:39 ` Sergei Shtylyov
2022-09-05 13:13 ` Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 08/12] PCI: renesas: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
2022-09-20 19:59 ` Bjorn Helgaas
2022-09-05 7:12 ` [PATCH v5 09/12] PCI: renesas: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 10/12] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 11/12] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 12/12] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Yoshihiro Shimoda
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