From: Biju Das <biju.das.jz@bp.renesas.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>, Lee Jones <lee@kernel.org>,
devicetree@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
linux-renesas-soc@vger.kernel.org
Subject: [PATCH RFC 4/8] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2UL MTU3 counter
Date: Mon, 26 Sep 2022 14:21:10 +0100 [thread overview]
Message-ID: <20220926132114.60396-5-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220926132114.60396-1-biju.das.jz@bp.renesas.com>
Document 16-bit and 32-bit phase counting mode support on
RZ/G2L MTU3 IP.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
index c1fae8e8d9f9..c4bcf28623d6 100644
--- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
+++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
@@ -192,6 +192,37 @@ properties:
"#size-cells":
const: 0
+patternProperties:
+ "^counter@[1-2]+$":
+ type: object
+
+ properties:
+ compatible:
+ const: renesas,rzg2l-mtu3-counter
+
+ reg:
+ description: Identify counter channels.
+ items:
+ enum: [ 1, 2 ]
+
+ renesas,32bit-phase-counting:
+ type: boolean
+ description: Enable 32-bit phase counting mode.
+
+ renesas,ext-input-phase-clock-select:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1 ]
+ default: 1
+ description: |
+ Selects the external clock pin for phase counting mode.
+ <0> : MTCLKA and MTCLKB are selected for the external phase clock.
+ <1> : MTCLKC and MTCLKD are selected for the external phase clock
+ (default)
+
+ required:
+ - compatible
+ - reg
+
required:
- compatible
- reg
@@ -270,6 +301,10 @@ examples:
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
+ counter@1 {
+ compatible = "renesas,rzg2l-mtu3-counter";
+ reg = <1>;
+ };
};
...
--
2.25.1
next prev parent reply other threads:[~2022-09-26 14:54 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-26 13:21 [PATCH RFC 0/8] Add RZ/G2L MTU3a MFD and Counter driver Biju Das
2022-09-26 13:21 ` [PATCH RFC 1/8] clk: renesas: r9a07g044: Add MTU3a clock and reset entry Biju Das
2022-09-26 13:21 ` [PATCH RFC 2/8] dt-bindings: mfd: Document RZ/G2L MTU3a bindings Biju Das
2022-10-03 7:50 ` Krzysztof Kozlowski
2022-10-03 8:18 ` Biju Das
2022-09-26 13:21 ` [PATCH RFC 3/8] mfd: Add RZ/G2L MTU3 driver Biju Das
2022-09-26 14:24 ` Philipp Zabel
2022-09-27 5:37 ` Biju Das
2022-09-26 13:21 ` Biju Das [this message]
2022-10-03 7:53 ` [PATCH RFC 4/8] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2UL MTU3 counter Krzysztof Kozlowski
2022-10-03 8:25 ` Biju Das
2022-09-26 13:21 ` [PATCH RFC 5/8] counter: Add RZ/G2L MTU3 counter driver Biju Das
2022-10-01 0:22 ` William Breathitt Gray
2022-10-05 10:29 ` Biju Das
2022-09-26 13:21 ` [PATCH RFC 6/8] arm64: dts: renesas: r9a07g044: Add MTU3a node Biju Das
2022-09-26 13:21 ` [PATCH RFC 7/8] arm64: dts: renesas: r9a07g054: " Biju Das
2022-09-26 13:21 ` [PATCH RFC 8/8] arm64: dts: renesas: rzg2l-smarc: [HACK] Enable MTU for 16-bit phase count testing Biju Das
2022-09-27 22:05 ` [PATCH RFC 0/8] Add RZ/G2L MTU3a MFD and Counter driver William Breathitt Gray
2022-09-28 6:14 ` Biju Das
2022-09-30 22:57 ` William Breathitt Gray
2022-10-01 16:45 ` Biju Das
2022-10-01 17:05 ` William Breathitt Gray
2022-10-01 17:12 ` Biju Das
2022-10-01 17:43 ` William Breathitt Gray
2022-10-01 18:03 ` Biju Das
2022-10-01 18:34 ` William Breathitt Gray
2022-10-01 18:51 ` Biju Das
2022-10-01 19:04 ` William Breathitt Gray
2022-10-01 19:21 ` Biju Das
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