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Wed, 9 Nov 2022 05:53:03 -0500 (EST) Date: Wed, 9 Nov 2022 11:53:01 +0100 From: Maxime Ripard To: Paul Cercueil Cc: Stephen Boyd , Maxime Coquelin , Chen-Yu Tsai , Daniel Vetter , Nicolas Ferre , Thierry Reding , Jaroslav Kysela , Shawn Guo , Fabio Estevam , Ulf Hansson , Claudiu Beznea , Michael Turquette , Dinh Nguyen , Chunyan Zhang , Manivannan Sadhasivam , Andreas =?utf-8?Q?F=C3=A4rber?= , Jonathan Hunter , Abel Vesa , Charles Keepax , Alessandro Zummo , Peter De Schrijver , Orson Zhai , Alexandre Torgue , Prashant Gaikwad , Liam Girdwood , Alexandre Belloni , Samuel Holland , Matthias Brugger , Richard Fitzgerald , Vinod Koul , NXP Linux Team , Sekhar Nori , Kishon Vijay Abraham I , Linus Walleij , Takashi Iwai , David Airlie , Luca Ceresoli , Jernej Skrabec , Pengutronix Kernel Team , Baolin Wang , David Lechner , Sascha Hauer , Mark Brown , Max Filippov , Geert Uytterhoeven , linux-stm32@st-md-mailman.stormreply.com, alsa-devel@alsa-project.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-mips@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-actions@lists.infradead.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno , patches@opensource.cirrus.com, linux-tegra@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: Re: [PATCH v2 56/65] clk: ingenic: cgu: Switch to determine_rate Message-ID: <20221109105301.ueus7o3b75j5yeff@houat> References: <20221018-clk-range-checks-fixes-v2-0-f6736dec138e@cerno.tech> <20221018-clk-range-checks-fixes-v2-56-f6736dec138e@cerno.tech> <80VTKR.CE8RVN8M3ZYK3@crapouillou.net> <20221104145946.orsyrhiqvypisl5j@houat> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hi Paul, On Sat, Nov 05, 2022 at 10:33:54AM +0000, Paul Cercueil wrote: > Hi Maxime, >=20 > Le ven. 4 nov. 2022 =E0 15:59:46 +0100, Maxime Ripard = a > =E9crit : > > Hi Paul, > >=20 > > On Fri, Nov 04, 2022 at 02:31:20PM +0000, Paul Cercueil wrote: > > > Le ven. 4 nov. 2022 =E0 14:18:13 +0100, Maxime Ripard > > > a > > > =E9crit : > > > > The Ingenic CGU clocks implements a mux with a set_parent hook, > > > but > > > > doesn't provide a determine_rate implementation. > > > > > > > > This is a bit odd, since set_parent() is there to, as its name > > > implies, > > > > change the parent of a clock. However, the most likely candidate > > > to > > > > trigger that parent change is a call to clk_set_rate(), with > > > > determine_rate() figuring out which parent is the best suited for > > > a > > > > given rate. > > > > > > > > The other trigger would be a call to clk_set_parent(), but it's > > > far less > > > > used, and it doesn't look like there's any obvious user for that > > > clock. > > > > > > > > So, the set_parent hook is effectively unused, possibly because > > > of an > > > > oversight. However, it could also be an explicit decision by the > > > > original author to avoid any reparenting but through an explicit > > > call to > > > > clk_set_parent(). > > > > > > > > The driver does implement round_rate() though, which means that > > > we can > > > > change the rate of the clock, but we will never get to change the > > > > parent. > > > > > > > > However, It's hard to tell whether it's been done on purpose or > > > not. > > > > > > > > Since we'll start mandating a determine_rate() implementation, > > > let's > > > > convert the round_rate() implementation to a determine_rate(), > > > which > > > > will also make the current behavior explicit. And if it was an > > > > oversight, the clock behaviour can be adjusted later on. > > >=20 > > > So it's partly on purpose, partly because I didn't know about > > > .determine_rate. > > >=20 > > > There's nothing odd about having a lonely .set_parent callback; in > > > my case > > > the clocks are parented from the device tree. > > >=20 > > > Having the clocks driver trigger a parent change when requesting a > > > rate > > > change sounds very dangerous, IMHO. My MMC controller can be > > > parented to the > > > external 48 MHz oscillator, and if the card requests 50 MHz, it > > > could switch > > > to one of the PLLs. That works as long as the PLLs don't change > > > rate, but if > > > one is configured as driving the CPU clock, it becomes messy. > > > The thing is, the clocks driver has no way to know whether or not > > > it is > > > "safe" to use a designated parent. > > >=20 > > > For that reason, in practice, I never actually want to have a clock > > > re-parented - it's almost always a bad idea vs. sticking to the > > > parent clock > > > configured in the DTS. > >=20 > > Yeah, and this is totally fine. But we need to be explicit about it. The > > determine_rate implementation I did in all the patches is an exact > > equivalent to the round_rate one if there was one. We will never ask to > > change the parent. > >=20 > > Given what you just said, I would suggest to set the > > CLK_SET_RATE_NO_REPARENT flag as well. >=20 > But that would introduce policy into the driver... I'm not sure why you're bringing policies into that discussion. There's plenty of policy in the driver already, and the current code doesn't do something that the old wasn't doing (implicitly). And there's plenty of policies in drivers in general. Whether you limit the rate or not, whether you allow reparenting or not, even the CLK_SET_RATE_NO_REPARENT flag mentioned above is a policy decision set by drivers. > The fact that I don't want the MMC parented to the PLLs, doesn't mean > that it's an invalid configuration per se. Sure, and that's another policy :) Maxime