* [PATCH v2 0/3] Add Versa3 clock generator support
@ 2023-03-09 16:55 Biju Das
2023-03-09 16:55 ` [PATCH v2 1/3] dt-bindings: clock: Add Renesas versa3 clock generator bindings Biju Das
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Biju Das @ 2023-03-09 16:55 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
devicetree, Prabhakar Mahadev Lad
The 5P35023 is a VersaClock programmable clock generator and
it provides 6 clk outputs {diff2, diff1, se3, se2, se1 and refin}.
It has an internal OTP memory allows the user to store the configuration
in the device. After power up, the user can change the device register
settings through the I2C interface when I2C mode is selected.
This driver is for overriding OTP default values during boot based on
a full register map from DT, and also minimal support to change the
parent of a output clock.
The motivation for developing this driver is for supporting 48KHz
playback/record with audio codec on RZ/G2L SMARC EVK.
On RZ/G2L SMARC EVK, By default audio mclk is connected to
11.2896 MHz clk which is multiple of 44.1KHz.
Please see the below default OTP configuration of Dividers connected to
output clocks.
DIV3 12.2880 MHz DIFF2--> Audio clk2
DIV5 11.2896 MHz SE1 --> Audio clk1
DIV5 11.2896 MHz SE2 --> Audio mck
DIV4 12 MHz SE3 --> This clk Not used
DIV1 25 MHz DIFF1-->Ethernet clk
Ref1-> 24MHz
With this setup, we won't be able to do 48KHz playback/record on audio codec,
as mck is always connected to 11.2896MHz clk.
But by programming the i2c, we can make use of DIV4 to generate 12.2880 MHz
and make that as parent of SE2 and there by supporting 48KHz playback/record.
A block diagram with modification can be find here[1]
[1]https://paste.pics/a253ce7cdc8720c3b5eb6953b97b25ff
DIV3 12.2880 MHz DIFF2--> Audio clk2
DIV5 11.2896 MHz SE1 --> Audio clk1
DIV5 11.2896 MHz | SE2 --> Audio mck
DIV4 12.2880 MHz |
DIV2 12 MHz SE3 --> This clk Not used
DIV1 25 MHz DIFF1--> Ethernet clk
Ref1-> 24MHz
The driver can read a full register map from the DT, and will use that
register map to initialize the clk generator when the system
boots.
and later, based on sampling rate, it switches the parent of SE2 and
support both 44.1 and 48 KHz playback/record at run time.
RFC->v2:
* Renamed the filename to match with compatible
* Added maintainers entry after title
* Removed the wrapping for the link to data sheet.
* Removed reg description
* Removed clock names
* Replaced minItems->maxItems in renesas,settings property
* Dropped assigned-clocks, assigned-clock-rates
* Dropped renesas,clock-divider-read-only and renesas,clock-flags
* Drooped clock handle part from example
* Dropped reg from example.
* Dropped consumer example
* Dropped header file <linux/clk.h> and removed all
consumer api's
* struct clk_parent_data used for assigning the parent names.
* Replaced initpointer->const init pointer in vc3_clk_register
* Replaced of_clk_add_hw_provider with devm_clk_add_hw_provider
* Dropped vc3_remove() callback.
Logs:
root@smarc-rzg2l:~# /audio_test.sh
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
xtal 0 0 0 24000000 0 0 50000 Y
ref 0 0 0 24000000 0 0 50000 Y
pfd1 0 0 0 24000000 0 0 50000 Y
pll1 0 0 0 600000000 0 0 50000 Y
div2 0 0 0 12000000 0 0 50000 Y
se3_mux 0 0 0 12000000 0 0 50000 Y
se3 0 0 0 12000000 0 0 50000 Y
div1_mux 0 0 0 600000000 0 0 50000 Y
div1 0 0 0 25000000 0 0 50000 Y
diff1_mux 0 0 0 25000000 0 0 50000 Y
diff1 0 0 0 25000000 0 0 50000 Y
pfd3_mux 0 0 0 24000000 0 0 50000 Y
pfd3 0 0 0 960000 0 0 50000 Y
pll3 0 0 0 564480000 0 0 50000 Y
div5 0 0 0 11289600 0 0 50000 Y
se1_mux 0 0 0 11289600 0 0 50000 Y
se1 0 0 0 11289600 0 0 50000 Y
se2_mux 0 0 0 11289600 0 0 50000 Y
se2 0 0 0 11289600 0 0 50000 Y
pfd2_mux 0 0 0 24000000 0 0 50000 Y
pfd2 0 0 0 24000000 0 0 50000 Y
pll2 0 0 0 491519897 0 0 50000 Y
div4_mux 0 0 0 491519897 0 0 50000 Y
div4 0 0 0 12287998 0 0 50000 Y
div3_mux 0 0 0 491519897 0 0 50000 Y
div3 0 0 0 12287998 0 0 50000 Y
diff2_mux 0 0 0 12287998 0 0 50000 Y
diff2 0 0 0 12287998 0 0 50000 Y
extal-clk 4 4 0 24000000 0 0 50000 Y
.pll5_foutpostdiv 0 0 0 24000000 0 0 50000 Y
M1 0 0 0 24000000 0 0 50000 Y
dsi_pll_clk 0 0 0 24000000 0 0 50000 N
.sel_pll5_4 0 0 0 24000000 0 0 50000 Y
DSI_DIV 0 0 0 24000000 0 0 50000 Y
M3 0 0 0 24000000 0 0 50000 Y
lcdc_clk_d 0 0 0 24000000 0 0 50000 N
dsi_vclk 0 0 0 24000000 0 0 50000 N
.pll5_fout1ph0 0 0 0 12000000 0 0 50000 Y
.pll6 2 2 0 500000000 0 0 50000 Y
.sel_gpu2 1 1 0 500000000 0 0 50000 Y
G 1 1 0 62500000 0 0 50000 Y
gpu_clk 1 2 0 62500000 0 0 50000 Y
.pll6_250 1 1 0 250000000 0 0 50000 Y
HP 2 2 0 250000000 0 0 50000 Y
.pll5 0 0 0 3000000000 0 0 50000 Y
.pll5_fout3 0 0 0 500000000 0 0 50000 Y
.pll5_250 0 0 0 250000000 0 0 50000 Y
.pll3 1 2 0 1600000000 0 0 50000 Y
.pll3_div2 1 1 0 800000000 0 0 50000 Y
.pll3_div2_4 3 3 0 200000000 0 0 50000 Y
M0 2 2 0 200000000 0 0 50000 Y
eth1_axi 1 1 0 200000000 0 0 50000 Y
eth0_axi 1 1 0 200000000 0 0 50000 Y
lcdc_a 0 0 0 200000000 0 0 50000 N
cru_aclk 0 0 0 200000000 0 0 50000 N
P1 11 12 0 200000000 0 0 50000 Y
usb_pclk 8 12 0 200000000 0 0 50000 Y
usb0_func 1 1 0 200000000 0 0 50000 Y
usb1_host 3 5 0 200000000 0 0 50000 Y
usb0_host 3 5 0 200000000 0 0 50000 Y
dsi_aclk 0 0 0 200000000 0 0 50000 N
gpu_ace_clk 0 1 0 200000000 0 0 50000 N
gpu_axi_clk 1 2 0 200000000 0 0 50000 Y
sdhi1_aclk 1 1 0 200000000 0 0 50000 Y
sdhi0_aclk 1 1 0 200000000 0 0 50000 Y
dmac_aclk 2 2 0 200000000 0 0 50000 Y
ia55_clk 2 2 0 200000000 0 0 50000 Y
gic 1 1 0 200000000 0 0 50000 Y
P1_DIV2 1 1 0 100000000 0 0 50000 Y
dmac_pclk 1 1 0 100000000 0 0 50000 Y
.pll3_div2_4_2 2 2 0 100000000 0 0 50000 Y
ZT 2 2 0 100000000 0 0 50000 Y
eth1_chi 1 1 0 100000000 0 0 50000 Y
eth0_chi 1 1 0 100000000 0 0 50000 Y
lcdc_p 0 0 0 100000000 0 0 50000 N
cru_pclk 0 0 0 100000000 0 0 50000 N
P2 1 1 0 100000000 0 0 50000 Y
dsi_pclk 0 0 0 100000000 0 0 50000 N
ia55_pclk 1 1 0 100000000 0 0 50000 Y
.pll3_div2_2 0 0 0 400000000 0 0 50000 Y
.pll3_533 0 1 0 533333333 0 0 50000 Y
M2 0 0 0 266666666 0 0 50000 Y
cru_vclk 0 0 0 266666666 0 0 50000 N
M2_DIV2 0 0 0 133333333 0 0 50000 Y
dsi_sys_clk 0 0 0 133333333 0 0 50000 N
cru_sysclk 0 0 0 133333333 0 0 50000 N
.sel_pll3_3 0 1 0 533333333 0 0 50000 Y
divpl3c 0 2 0 266666667 0 0 50000 Y
SPI1 0 1 0 66666666 0 0 50000 Y
spi_clk2 0 1 0 66666666 0 0 50000 N
SPI0 0 1 0 133333333 0 0 50000 Y
spi_clk 0 1 0 133333333 0 0 50000 N
.pll3_400 0 0 0 400000000 0 0 50000 Y
.pll2 2 2 0 1600000000 0 0 50000 Y
.clk_533 2 2 0 533333333 0 0 50000 Y
sd1 2 2 0 533333333 0 0 50000 Y
sdhi1_clk_hs 1 1 0 533333333 0 0 50000 Y
SD1_DIV4 2 2 0 133333333 0 0 50000 Y
sdhi1_imclk2 2 2 0 133333333 0 0 50000 Y
sdhi1_imclk 1 1 0 133333333 0 0 50000 Y
sd0 2 2 0 533333333 0 0 50000 Y
sdhi0_clk_hs 1 1 0 533333333 0 0 50000 Y
SD0_DIV4 2 2 0 133333333 0 0 50000 Y
sdhi0_imclk2 2 2 0 133333333 0 0 50000 Y
sdhi0_imclk 1 1 0 133333333 0 0 50000 Y
.clk_266 0 0 0 266666666 0 0 50000 Y
.clk_800 0 0 0 800000000 0 0 50000 Y
.clk_400 0 0 0 400000000 0 0 50000 Y
.pll2_div2 2 2 0 800000000 0 0 50000 Y
.pll2_div2_10 1 1 0 80000000 0 0 50000 Y
TSU 1 2 0 80000000 0 0 50000 Y
tsu_pclk 1 1 0 80000000 0 0 50000 Y
adc_adclk 0 1 0 80000000 0 0 50000 N
.pll2_div2_8 1 1 0 100000000 0 0 50000 Y
P0 6 14 0 100000000 0 0 50000 Y
adc_pclk 0 1 0 100000000 0 0 50000 N
canfd 1 2 0 100000000 0 0 50000 Y
rspi2 0 0 0 100000000 0 0 50000 N
rspi1 0 1 0 100000000 0 0 50000 N
rspi0 0 0 0 100000000 0 0 50000 N
sci1 0 0 0 100000000 0 0 50000 N
sci0 0 0 0 100000000 0 0 50000 N
scif4 0 0 0 100000000 0 0 50000 N
scif3 0 0 0 100000000 0 0 50000 N
scif2 0 1 0 100000000 0 0 50000 N
scif1 0 0 0 100000000 0 0 50000 N
scif0 2 2 0 100000000 0 0 50000 Y
i2c3 0 1 0 100000000 0 0 50000 N
i2c2 0 0 0 100000000 0 0 50000 N
i2c1 0 1 0 100000000 0 0 50000 N
i2c0 0 1 0 100000000 0 0 50000 N
ssi3_sfr 0 0 0 100000000 0 0 50000 N
ssi3_pclk 0 0 0 100000000 0 0 50000 N
ssi2_sfr 0 0 0 100000000 0 0 50000 N
ssi2_pclk 0 0 0 100000000 0 0 50000 N
ssi1_sfr 0 0 0 100000000 0 0 50000 N
ssi1_pclk 0 0 0 100000000 0 0 50000 N
ssi0_sfr 1 1 0 100000000 0 0 50000 Y
ssi0_pclk 1 1 0 100000000 0 0 50000 Y
wdt1_pclk 0 1 0 100000000 0 0 50000 N
wdt0_pclk 0 1 0 100000000 0 0 50000 N
poeg_d_clkp 0 0 0 100000000 0 0 50000 N
poeg_c_clkp 0 0 0 100000000 0 0 50000 N
poeg_b_clkp 0 0 0 100000000 0 0 50000 N
poeg_a_clkp 0 0 0 100000000 0 0 50000 N
gpt_pclk 0 0 0 100000000 0 0 50000 N
mtu_x_mck 0 0 0 100000000 0 0 50000 N
ostm2_pclk 1 2 0 100000000 0 0 50000 Y
ostm1_pclk 1 2 0 100000000 0 0 50000 Y
ostm0_pclk 0 0 0 100000000 0 0 50000 N
P0_DIV2 0 0 0 50000000 0 0 50000 Y
.pll2_533 0 0 0 533333333 0 0 50000 Y
.pll2_533_div2 0 0 0 266666666 0 0 50000 Y
.div_dsi_lpclk 0 0 0 16666667 0 0 50000 Y
M4 0 0 0 16666667 0 0 50000 Y
dsi_lpclk 0 0 0 16666667 0 0 50000 N
.pll1 0 0 0 1200000000 0 0 50000 Y
I 0 0 0 1200000000 0 0 50000 Y
.osc_div1000 0 0 0 24000 0 0 50000 Y
.osc 1 3 0 24000000 0 0 50000 Y
gpio 1 2 0 24000000 0 0 50000 Y
wdt1_clk 0 1 0 24000000 0 0 50000 N
wdt0_clk 0 1 0 24000000 0 0 50000 N
can-clk 0 0 0 0 0 0 50000 Y
audio2-clk 0 0 0 12288000 0 0 50000 Y
audio1-clk 0 0 0 11289600 0 0 50000 Y
playback 48000 kHz sample
speaker-test 1.2.1
Playback device is hw:0,0
Stream parameters are 48000Hz, S16_LE, 2 channels
Using 16 octaves of pink noise
Rate set to 48000Hz (requested 48000Hz)
Buffer size range from 8 to 8192
Period size range from 8 to 2048
Using max buffer size 8192
Periods = 4
was set period_size = 2048
was set buffer_size = 8192
0 - Front Left
00: 80
01: 00
02: 11
03: 19
04: 4c
05: 02
06: 23
07: 7f
08: 83
09: 19
0a: 08
0b: a9
0c: 5f
0d: 25
0e: 24
0f: bf
10: 00
11: 14
12: 7a
13: e1
14: 00
15: 00
16: 00
17: 00
18: 01
19: 55
1a: 59
1b: bb
1c: 3f
1d: 30
1e: 90
1f: f6
20: 80
21: b0
22: 45
23: c4
24: 95
Read at address 0x10049C00 (0xffff9a615c00): 0x300B4022
pfd2 1 1 0 24000000 0 0 50000 Y
pll2 1 1 0 491519897 0 0 50000 Y
div4_mux 1 1 0 491519897 0 0 50000 Y
div4 1 1 0 12287998 0 0 50000 Y
se2_mux 1 1 0 12287998 0 0 50000 Y
se2 1 1 0 12287998 0 0 50000 Y
1 - Front Right
playback 44100 kHz sample
speaker-test 1.2.1
Playback device is hw:0,0
Stream parameters are 44100Hz, S16_LE, 2 channels
Using 16 octaves of pink noise
Rate set to 44100Hz (requested 44100Hz)
Buffer size range from 8 to 8192
Period size range from 8 to 2048
Using max buffer size 8192
Periods = 4
was set period_size = 2048
was set buffer_size = 8192
0 - Front Left
/audio_test.sh: line 2: 187 Killed speaker-test -D hw:0,0 -c 2 -r $1
00: 80
01: 00
02: 11
03: 19
04: 4c
05: 02
06: 23
07: 7f
08: 83
09: 19
0a: 08
0b: a9
0c: 5f
0d: 25
0e: 24
0f: bf
10: 00
11: 14
12: 7a
13: e1
14: 00
15: 00
16: 00
17: 00
18: 01
19: 55
1a: 59
1b: bb
1c: 3f
1d: 30
1e: 90
1f: b6
20: 80
21: b0
22: 45
23: c4
24: 95
Read at address 0x10049C00 (0xffffb7957c00): 0x700B4022
pfd3_mux 1 1 0 24000000 0 0 50000 Y
pfd3 1 1 0 960000 0 0 50000 Y
pll3 1 1 0 564480000 0 0 50000 Y
div5 1 1 0 11289600 0 0 50000 Y
se2_mux 1 1 0 11289600 0 0 50000 Y
se2 1 1 0 11289600 0 0 50000 Y
Biju Das (3):
dt-bindings: clock: Add Renesas versa3 clock generator bindings
drivers: clk: Add support for versa3 clock driver
arm64: dts: renesas: rzg2l-smarc: Use versa3 clk for audio mclk
.../bindings/clock/renesas,5p35023.yaml | 90 ++
.../boot/dts/renesas/rz-smarc-common.dtsi | 7 -
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 32 +
drivers/clk/Kconfig | 9 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-versaclock3.c | 1139 +++++++++++++++++
6 files changed, 1271 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
create mode 100644 drivers/clk/clk-versaclock3.c
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/3] dt-bindings: clock: Add Renesas versa3 clock generator bindings
2023-03-09 16:55 [PATCH v2 0/3] Add Versa3 clock generator support Biju Das
@ 2023-03-09 16:55 ` Biju Das
2023-03-10 8:47 ` Krzysztof Kozlowski
2023-03-09 16:55 ` [PATCH v2 2/3] drivers: clk: Add support for versa3 clock driver Biju Das
2023-03-09 16:55 ` [PATCH v2 3/3] arm64: dts: renesas: rzg2l-smarc: Use versa3 clk for audio mclk Biju Das
2 siblings, 1 reply; 9+ messages in thread
From: Biju Das @ 2023-03-09 16:55 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
devicetree, Prabhakar Mahadev Lad
Document Renesas versa3 clock generator(5P35023) bindings.
The 5P35023 is a VersaClock programmable clock generator and
is designed for low-power, consumer, and high-performance PCI
Express applications. The 5P35023 device is a three PLL
architecture design, and each PLL is individually programmable
and allowing for up to 6 unique frequency outputs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
RFC->v2:
* Renamed the filename to match with compatible
* Added maintainers entry after title
* Removed the wrapping for the link to data sheet.
* Removed reg description
* Removed clock names
* Replaced minItems->maxItems in renesas,settings property
* Dropped assigned-clocks, assigned-clock-rates
* Dropped renesas,clock-divider-read-only and renesas,clock-flags
* Drooped clock handle part from example
* Dropped reg from example.
* Dropped consumer example
---
.../bindings/clock/renesas,5p35023.yaml | 90 +++++++++++++++++++
1 file changed, 90 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
new file mode 100644
index 000000000000..ee4afc2ea67b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ The 5P35023 is a VersaClock programmable clock generator and
+ is designed for low-power, consumer, and high-performance PCI
+ express applications. The 5P35023 device is a three PLL
+ architecture design, and each PLL is individually programmable
+ and allowing for up to 6 unique frequency outputs.
+
+ An internal OTP memory allows the user to store the configuration
+ in the device. After power up, the user can change the device register
+ settings through the I2C interface when I2C mode is selected.
+
+ The driver can read a full register map from the DT, and will use that
+ register map to initialize the attached part (via I2C) when the system
+ boots. Any configuration not supported by the common clock framework
+ must be done via the full register map, including optimized settings.
+
+ Link to datasheet: |
+ https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator
+
+properties:
+ compatible:
+ enum:
+ - renesas,5p35023
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ renesas,settings:
+ description: Optional, complete register map of the device.
+ Optimized settings for the device must be provided in full
+ and are written during initialization.
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+ maxItems: 37
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ versa3: clock-generator@68 {
+ compatible = "renesas,5p35023";
+ reg = <0x68>;
+ #clock-cells = <1>;
+
+ clocks = <&x1_x2>;
+
+ renesas,settings = [
+ 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
+ 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
+ 80 b0 45 c4 95
+ ];
+
+ assigned-clocks = <&versa3 0>,
+ <&versa3 1>,
+ <&versa3 2>,
+ <&versa3 3>,
+ <&versa3 4>,
+ <&versa3 5>;
+ assigned-clock-rates = <12288000>, <25000000>,
+ <12000000>, <11289600>,
+ <11289600>, <24000000>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/3] drivers: clk: Add support for versa3 clock driver
2023-03-09 16:55 [PATCH v2 0/3] Add Versa3 clock generator support Biju Das
2023-03-09 16:55 ` [PATCH v2 1/3] dt-bindings: clock: Add Renesas versa3 clock generator bindings Biju Das
@ 2023-03-09 16:55 ` Biju Das
2023-03-21 23:16 ` Stephen Boyd
2023-03-09 16:55 ` [PATCH v2 3/3] arm64: dts: renesas: rzg2l-smarc: Use versa3 clk for audio mclk Biju Das
2 siblings, 1 reply; 9+ messages in thread
From: Biju Das @ 2023-03-09 16:55 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, linux-clk, Geert Uytterhoeven, Prabhakar Mahadev Lad,
linux-renesas-soc
Add support for Renesas versa3 clock driver(5p35023).
The clock generator provides 6 output clocks.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
RFC->v2:
* Dropped header file <linux/clk.h> and removed all
consumer api's
* struct clk_parent_data used for assigning the parent names.
* Replaced initpointer->const init pointer in vc3_clk_register
* Replaced of_clk_add_hw_provider with devm_clk_add_hw_provider
* Dropped vc3_remove() callback.
---
drivers/clk/Kconfig | 9 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-versaclock3.c | 1139 +++++++++++++++++++++++++++++++++
3 files changed, 1149 insertions(+)
create mode 100644 drivers/clk/clk-versaclock3.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index b6c5bf69a2b2..4dfa44cf5289 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -367,6 +367,15 @@ config COMMON_CLK_RS9_PCIE
This driver supports the Renesas 9-series PCIe clock generator
models 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ.
+config COMMON_CLK_VC3
+ tristate "Clock driver for Renesas VersaClock 3 devices"
+ depends on I2C
+ depends on OF
+ select REGMAP_I2C
+ help
+ This driver supports the Renesas VersaClock 3 programmable clock
+ generators.
+
config COMMON_CLK_VC5
tristate "Clock driver for IDT VersaClock 5,6 devices"
depends on I2C
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e3ca0d058a25..e7aa4f81863c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -72,6 +72,7 @@ obj-$(CONFIG_COMMON_CLK_TPS68470) += clk-tps68470.o
obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o
+obj-$(CONFIG_COMMON_CLK_VC3) += clk-versaclock3.o
obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
obj-$(CONFIG_COMMON_CLK_VC7) += clk-versaclock7.o
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c
new file mode 100644
index 000000000000..6c5c8b37f6af
--- /dev/null
+++ b/drivers/clk/clk-versaclock3.c
@@ -0,0 +1,1139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Renesas Versaclock 3
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/i2c.h>
+#include <linux/limits.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+
+#define NUM_CONFIG_REGISTERS 37
+
+#define VC3_GENERAL_CTR 0x0
+#define VC3_GENERAL_CTR_DIV1_SRC_SEL BIT(3)
+#define VC3_GENERAL_CTR_PLL3_REFIN_SEL BIT(2)
+
+#define VC3_PLL3_M_DIVIDER 0x3
+#define VC3_PLL3_M_DIV1 BIT(7)
+#define VC3_PLL3_M_DIV2 BIT(6)
+#define VC3_PLL3_M_DIV(n) ((n) & GENMASK(5, 0))
+
+#define VC3_PLL3_N_DIVIDER 0x4
+#define VC3_PLL3_LOOP_FILTER_N_DIV_MSB 0x5
+
+#define VC3_PLL3_CHARGE_PUMP_CTRL 0x6
+#define VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL BIT(7)
+
+#define VC3_PLL1_CTRL_OUTDIV5 0x7
+#define VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER BIT(7)
+
+#define VC3_PLL1_M_DIVIDER 0x8
+#define VC3_PLL1_M_DIV1 BIT(7)
+#define VC3_PLL1_M_DIV2 BIT(6)
+#define VC3_PLL1_M_DIV(n) ((n) & GENMASK(5, 0))
+
+#define VC3_PLL1_VCO_N_DIVIDER 0x9
+#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0x0a
+
+#define VC3_OUT_DIV1_DIV2_CTRL 0xf
+
+#define VC3_PLL2_FB_INT_DIV_MSB 0x10
+#define VC3_PLL2_FB_INT_DIV_LSB 0x11
+#define VC3_PLL2_FB_FRC_DIV_MSB 0x12
+#define VC3_PLL2_FB_FRC_DIV_LSB 0x13
+
+#define VC3_PLL2_M_DIVIDER 0x1a
+#define VC3_PLL2_MDIV_DOUBLER BIT(7)
+#define VC3_PLL2_M_DIV1 BIT(6)
+#define VC3_PLL2_M_DIV2 BIT(5)
+#define VC3_PLL2_M_DIV(n) ((n) & GENMASK(4, 0))
+
+#define VC3_OUT_DIV3_DIV4_CTRL 0x1b
+
+#define VC3_PLL_OP_CTRL 0x1c
+#define VC3_PLL_OP_CTRL_PLL2_REFIN_SEL 6
+
+#define VC3_OUTPUT_CTR 0x1d
+#define VC3_OUTPUT_CTR_DIV4_SRC_SEL BIT(3)
+
+#define VC3_SE2_CTRL_REG0 0x1f
+#define VC3_SE2_CTRL_REG0_SE2_CLK_SEL BIT(6)
+
+#define VC3_SE3_DIFF1_CTRL_REG 0x21
+#define VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL BIT(6)
+
+#define VC3_DIFF1_CTRL_REG 0x22
+#define VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL BIT(7)
+
+#define VC3_DIFF2_CTRL_REG 0x23
+#define VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL BIT(7)
+
+#define VC3_SE1_DIV4_CTRL 0x24
+#define VC3_SE1_DIV4_CTRL_SE1_CLK_SEL BIT(3)
+
+#define VC3_PLL1_VCO_MIN 300000000UL
+#define VC3_PLL1_VCO_MAX 600000000UL
+
+#define VC3_PLL2_VCO_MIN 400000000UL
+#define VC3_PLL2_VCO_MAX 1200000000UL
+
+#define VC3_PLL3_VCO_MIN 300000000UL
+#define VC3_PLL3_VCO_MAX 800000000UL
+
+#define VC3_2_POW_16 (U16_MAX + 1)
+#define VC3_DIV_MASK(width) ((1 << (width)) - 1)
+
+struct vc3_driver_data;
+
+enum vc3_pfd_mux {
+ VC3_PFD2_MUX,
+ VC3_PFD3_MUX,
+};
+
+enum vc3_pfd {
+ VC3_PFD1,
+ VC3_PFD2,
+ VC3_PFD3,
+};
+
+enum vc3_pll {
+ VC3_PLL1,
+ VC3_PLL2,
+ VC3_PLL3,
+};
+
+enum vc3_div_mux {
+ VC3_DIV1_MUX,
+ VC3_DIV3_MUX,
+ VC3_DIV4_MUX,
+};
+
+enum vc3_div {
+ VC3_DIV1,
+ VC3_DIV2,
+ VC3_DIV3,
+ VC3_DIV4,
+ VC3_DIV5,
+};
+
+enum vc3_clk_mux {
+ VC3_DIFF2_MUX,
+ VC3_DIFF1_MUX,
+ VC3_SE3_MUX,
+ VC3_SE2_MUX,
+ VC3_SE1_MUX,
+};
+
+enum vc3_clk {
+ VC3_DIFF2,
+ VC3_DIFF1,
+ VC3_SE3,
+ VC3_SE2,
+ VC3_SE1,
+ VC3_REF,
+};
+
+struct vc3_clk_data {
+ const char * const name;
+ u8 offs;
+ u8 bitmsk;
+};
+
+struct vc3_pfd_data {
+ const char * const name;
+ u8 offs;
+ u8 mdiv1_bitmsk;
+ u8 mdiv2_bitmsk;
+};
+
+struct vc3_pll_data {
+ const char * const name;
+ u8 int_div_msb_offs;
+ u8 int_div_lsb_offs;
+ unsigned long vco_min;
+ unsigned long vco_max;
+};
+
+struct vc3_div_data {
+ const char * const name;
+ u8 offs;
+ const struct clk_div_table *table;
+ u8 shift;
+ u8 width;
+};
+
+static const struct clk_div_table div1_divs[] = {
+ { .val = 0, .div = 1, }, { .val = 1, .div = 4, },
+ { .val = 2, .div = 5, }, { .val = 3, .div = 6, },
+ { .val = 4, .div = 2, }, { .val = 5, .div = 8, },
+ { .val = 6, .div = 10, }, { .val = 7, .div = 12, },
+ { .val = 8, .div = 4, }, { .val = 9, .div = 16, },
+ { .val = 10, .div = 20, }, { .val = 11, .div = 24, },
+ { .val = 12, .div = 8, }, { .val = 13, .div = 32, },
+ { .val = 14, .div = 40, }, { .val = 15, .div = 48, },
+ {}
+};
+
+static const struct clk_div_table div245_divs[] = {
+ { .val = 0, .div = 1, }, { .val = 1, .div = 3, },
+ { .val = 2, .div = 5, }, { .val = 3, .div = 10, },
+ { .val = 4, .div = 2, }, { .val = 5, .div = 6, },
+ { .val = 6, .div = 10, }, { .val = 7, .div = 20, },
+ { .val = 8, .div = 4, }, { .val = 9, .div = 12, },
+ { .val = 10, .div = 20, }, { .val = 11, .div = 40, },
+ { .val = 12, .div = 5, }, { .val = 13, .div = 15, },
+ { .val = 14, .div = 25, }, { .val = 15, .div = 50, },
+ {}
+};
+
+static const struct clk_div_table div3_divs[] = {
+ { .val = 0, .div = 1, }, { .val = 1, .div = 3, },
+ { .val = 2, .div = 5, }, { .val = 3, .div = 10, },
+ { .val = 4, .div = 2, }, { .val = 5, .div = 6, },
+ { .val = 6, .div = 10, }, { .val = 7, .div = 20, },
+ { .val = 8, .div = 4, }, { .val = 9, .div = 12, },
+ { .val = 10, .div = 20, }, { .val = 11, .div = 40, },
+ { .val = 12, .div = 8, }, { .val = 13, .div = 24, },
+ { .val = 14, .div = 40, }, { .val = 15, .div = 80, },
+ {}
+};
+
+static const char * const vc3_fin_name = "xtal";
+
+static const char * const vc3_pfd_mux_names[] = {
+ [VC3_PFD2_MUX] = "pfd2_mux",
+ [VC3_PFD3_MUX] = "pfd3_mux"
+};
+
+static const char * const vc3_pfd_names[] = {
+ [VC3_PFD1] = "pfd1",
+ [VC3_PFD2] = "pfd2",
+ [VC3_PFD3] = "pfd3"
+};
+
+static const char * const vc3_pll_names[] = {
+ [VC3_PLL1] = "pll1",
+ [VC3_PLL2] = "pll2",
+ [VC3_PLL3] = "pll3"
+};
+
+static const char * const vc3_div_mux_names[] = {
+ [VC3_DIV1_MUX] = "div1_mux",
+ [VC3_DIV3_MUX] = "div3_mux",
+ [VC3_DIV4_MUX] = "div4_mux"
+};
+
+static const char * const vc3_div_names[] = {
+ [VC3_DIV1] = "div1",
+ [VC3_DIV2] = "div2",
+ [VC3_DIV3] = "div3",
+ [VC3_DIV4] = "div4",
+ [VC3_DIV5] = "div5"
+};
+
+static const char * const vc3_clk_mux_names[] = {
+ [VC3_DIFF2_MUX] = "diff2_mux",
+ [VC3_DIFF1_MUX] = "diff1_mux",
+ [VC3_SE3_MUX] = "se3_mux",
+ [VC3_SE2_MUX] = "se2_mux",
+ [VC3_SE1_MUX] = "se1_mux"
+};
+
+static const char * const vc3_clk_out_names[] = {
+ [VC3_DIFF2] = "diff2",
+ [VC3_DIFF1] = "diff1",
+ [VC3_SE3] = "se3",
+ [VC3_SE2] = "se2",
+ [VC3_SE1] = "se1",
+ [VC3_REF] = "ref"
+};
+
+static const struct clk_parent_data pfdmux_p[] = {
+ { .fw_name = vc3_fin_name, .name = vc3_fin_name },
+ { .fw_name = "div2", .name = "div2" }
+};
+
+static const struct clk_parent_data pfd_p[] = {
+ { .fw_name = vc3_fin_name, .name = vc3_fin_name },
+ { .fw_name = "pfd2_mux", .name = "pfd2_mux" },
+ { .fw_name = "pfd3_mux", .name = "pfd3_mux" }
+};
+
+static const struct clk_parent_data pll_p[] = {
+ { .fw_name = "pfd1", .name = "pfd1" },
+ { .fw_name = "pfd2", .name = "pfd2" },
+ { .fw_name = "pfd3", .name = "pfd3" }
+};
+
+static const struct clk_parent_data divmux_p[][2] = {
+ {
+ { .fw_name = "pll1", .name = "pll1" },
+ { .fw_name = "xtal", .name = vc3_fin_name }
+ },
+ {
+ { .fw_name = "pll2", .name = "pll2" },
+ { .fw_name = "pll3", .name = "pll3" }
+ },
+ {
+ { .fw_name = "pll2", .name = "pll2" },
+ { .fw_name = vc3_fin_name, .name = vc3_fin_name }
+ }
+};
+
+static const struct clk_parent_data div_p[] = {
+ { .fw_name = "div1_mux", .name = "div1_mux" },
+ { .fw_name = "pll1", .name = "pll1" },
+ { .fw_name = "div3_mux", .name = "div3_mux" },
+ { .fw_name = "div4_mux", .name = "div4_mux" },
+ { .fw_name = "pll3", .name = "pll3" }
+};
+
+static const struct clk_parent_data clkmux_p[][2] = {
+ {
+ { .fw_name = "div1", .name = "div1" },
+ { .fw_name = "div3", .name = "div3" }
+ },
+ {
+ { .fw_name = "div1", .name = "div1" },
+ { .fw_name = "div3", .name = "div3" }
+ },
+ {
+ { .fw_name = "div2", .name = "div2" },
+ { .fw_name = "div4", .name = "div4" }
+ },
+ {
+ { .fw_name = "div5", .name = "div5" },
+ { .fw_name = "div4", .name = "div4" }
+ },
+ {
+ { .fw_name = "div5", .name = "div5" },
+ { .fw_name = "div4", .name = "div4" }
+ }
+};
+
+static const struct clk_parent_data clkout_p[] = {
+ { .fw_name = "diff2_mux", .name = "diff2_mux" },
+ { .fw_name = "diff1_mux", .name = "diff1_mux" },
+ { .fw_name = "se3_mux", .name = "se3_mux" },
+ { .fw_name = "se2_mux", .name = "se2_mux" },
+ { .fw_name = "se1_mux", .name = "se1_mux" },
+ { .fw_name = vc3_fin_name, .name = vc3_fin_name }
+};
+
+static const struct vc3_clk_data pfd_mux_data[] = {
+ [VC3_PFD2_MUX] = {
+ .name = vc3_pfd_mux_names[VC3_PFD2_MUX],
+ .offs = VC3_PLL_OP_CTRL,
+ .bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL)
+ },
+ [VC3_PFD3_MUX] = {
+ .name = vc3_pfd_mux_names[VC3_PFD3_MUX],
+ .offs = VC3_GENERAL_CTR,
+ .bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL)
+ }
+};
+
+static const struct vc3_pfd_data pfd_data[] = {
+ [VC3_PFD1] = {
+ .name = vc3_pfd_names[VC3_PFD1],
+ .offs = VC3_PLL1_M_DIVIDER,
+ .mdiv1_bitmsk = VC3_PLL1_M_DIV1,
+ .mdiv2_bitmsk = VC3_PLL1_M_DIV2
+ },
+ [VC3_PFD2] = {
+ .name = vc3_pfd_names[VC3_PFD2],
+ .offs = VC3_PLL2_M_DIVIDER,
+ .mdiv1_bitmsk = VC3_PLL2_M_DIV1,
+ .mdiv2_bitmsk = VC3_PLL2_M_DIV2
+ },
+ [VC3_PFD3] = {
+ .name = vc3_pfd_names[VC3_PFD3],
+ .offs = VC3_PLL3_M_DIVIDER,
+ .mdiv1_bitmsk = VC3_PLL3_M_DIV1,
+ .mdiv2_bitmsk = VC3_PLL3_M_DIV2
+ }
+};
+
+static const struct vc3_pll_data pll_data[] = {
+ [VC3_PLL1] = {
+ .name = vc3_pll_names[VC3_PLL1],
+ .int_div_msb_offs = VC3_PLL1_LOOP_FILTER_N_DIV_MSB,
+ .int_div_lsb_offs = VC3_PLL1_VCO_N_DIVIDER,
+ .vco_min = VC3_PLL1_VCO_MIN,
+ .vco_max = VC3_PLL1_VCO_MAX
+ },
+ [VC3_PLL2] = {
+ .name = vc3_pll_names[VC3_PLL2],
+ .int_div_msb_offs = VC3_PLL2_FB_INT_DIV_MSB,
+ .int_div_lsb_offs = VC3_PLL2_FB_INT_DIV_LSB,
+ .vco_min = VC3_PLL2_VCO_MIN,
+ .vco_max = VC3_PLL2_VCO_MAX
+ },
+ [VC3_PLL3] = {
+ .name = vc3_pll_names[VC3_PLL3],
+ .int_div_msb_offs = VC3_PLL3_LOOP_FILTER_N_DIV_MSB,
+ .int_div_lsb_offs = VC3_PLL3_N_DIVIDER,
+ .vco_min = VC3_PLL3_VCO_MIN,
+ .vco_max = VC3_PLL3_VCO_MAX
+ }
+};
+
+static const struct vc3_clk_data div_mux_data[] = {
+ [VC3_DIV1_MUX] = {
+ .name = vc3_div_mux_names[VC3_DIV1_MUX],
+ .offs = VC3_GENERAL_CTR,
+ .bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL
+ },
+ [VC3_DIV3_MUX] = {
+ .name = vc3_div_mux_names[VC3_DIV3_MUX],
+ .offs = VC3_PLL3_CHARGE_PUMP_CTRL,
+ .bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL
+ },
+ [VC3_DIV4_MUX] = {
+ .name = vc3_div_mux_names[VC3_DIV4_MUX],
+ .offs = VC3_OUTPUT_CTR,
+ .bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL
+ }
+};
+
+static const struct vc3_div_data div_data[] = {
+ [VC3_DIV1] = {
+ .name = vc3_div_names[VC3_DIV1],
+ .offs = VC3_OUT_DIV1_DIV2_CTRL,
+ .table = div1_divs,
+ .shift = 4,
+ .width = 4
+ },
+ [VC3_DIV2] = {
+ .name = vc3_div_names[VC3_DIV2],
+ .offs = VC3_OUT_DIV1_DIV2_CTRL,
+ .table = div245_divs,
+ .shift = 0,
+ .width = 4
+ },
+ [VC3_DIV3] = {
+ .name = vc3_div_names[VC3_DIV3],
+ .offs = VC3_OUT_DIV3_DIV4_CTRL,
+ .table = div3_divs,
+ .shift = 4,
+ .width = 4
+ },
+ [VC3_DIV4] = {
+ .name = vc3_div_names[VC3_DIV4],
+ .offs = VC3_OUT_DIV3_DIV4_CTRL,
+ .table = div245_divs,
+ .shift = 0,
+ .width = 4
+ },
+ [VC3_DIV5] = {
+ .name = vc3_div_names[VC3_DIV5],
+ .offs = VC3_PLL1_CTRL_OUTDIV5,
+ .table = div245_divs,
+ .shift = 0,
+ .width = 4
+ }
+};
+
+static const struct vc3_clk_data clk_mux_data[] = {
+ [VC3_DIFF2_MUX] = {
+ .name = vc3_clk_mux_names[VC3_DIFF2_MUX],
+ .offs = VC3_DIFF2_CTRL_REG,
+ .bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL
+ },
+ [VC3_DIFF1_MUX] = {
+ .name = vc3_clk_mux_names[VC3_DIFF1_MUX],
+ .offs = VC3_DIFF1_CTRL_REG,
+ .bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL
+ },
+ [VC3_SE3_MUX] = {
+ .name = vc3_clk_mux_names[VC3_SE3_MUX],
+ .offs = VC3_SE3_DIFF1_CTRL_REG,
+ .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL
+ },
+ [VC3_SE2_MUX] = {
+ .name = vc3_clk_mux_names[VC3_SE2_MUX],
+ .offs = VC3_SE2_CTRL_REG0,
+ .bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL
+ },
+ [VC3_SE1_MUX] = {
+ .name = vc3_clk_mux_names[VC3_SE1_MUX],
+ .offs = VC3_SE1_DIV4_CTRL,
+ .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL
+ }
+};
+
+static const struct vc3_clk_data clk_out_data[] = {
+ [VC3_DIFF2] = { .name = vc3_clk_out_names[VC3_DIFF2] },
+ [VC3_DIFF1] = { .name = vc3_clk_out_names[VC3_DIFF1] },
+ [VC3_SE3] = { .name = vc3_clk_out_names[VC3_SE3] },
+ [VC3_SE2] = { .name = vc3_clk_out_names[VC3_SE2] },
+ [VC3_SE1] = { .name = vc3_clk_out_names[VC3_SE1] },
+ [VC3_REF] = { .name = vc3_clk_out_names[VC3_REF] }
+};
+
+struct vc3_hw_data {
+ struct clk_hw hw;
+ struct vc3_driver_data *vc3;
+ const void *data;
+ unsigned int num;
+ u32 div_int;
+ u32 div_frc;
+ u8 flags;
+};
+
+struct vc3_driver_data {
+ struct i2c_client *client;
+ struct regmap *regmap;
+
+ struct vc3_hw_data clk_pfd_mux[ARRAY_SIZE(pfd_mux_data)];
+ struct vc3_hw_data clk_pfd[ARRAY_SIZE(pfd_data)];
+ struct vc3_hw_data clk_pll[ARRAY_SIZE(pll_data)];
+ struct vc3_hw_data clk_div_mux[ARRAY_SIZE(div_mux_data)];
+ struct vc3_hw_data clk_div[ARRAY_SIZE(div_data)];
+ struct vc3_hw_data clk_mux[ARRAY_SIZE(clk_mux_data)];
+ struct vc3_hw_data clk_out[ARRAY_SIZE(clk_out_data)];
+};
+
+static unsigned char vc3_pfd_mux_get_parent(struct clk_hw *hw)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_clk_data *pfd_mux = hwdata->data;
+ struct vc3_driver_data *vc3 = hwdata->vc3;
+ u32 src;
+
+ regmap_read(vc3->regmap, pfd_mux->offs, &src);
+
+ return !!(src & pfd_mux->bitmsk);
+}
+
+static int vc3_pfd_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_clk_data *pfd_mux = hwdata->data;
+ struct vc3_driver_data *vc3 = hwdata->vc3;
+
+ regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk,
+ index ? pfd_mux->bitmsk : 0);
+ return 0;
+}
+
+static const struct clk_ops vc3_pfd_mux_ops = {
+ .set_parent = vc3_pfd_mux_set_parent,
+ .get_parent = vc3_pfd_mux_get_parent,
+};
+
+static unsigned long vc3_pfd_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_pfd_data *pfd = hwdata->data;
+ struct vc3_driver_data *vc3 = hwdata->vc3;
+ unsigned int prediv, premul;
+ unsigned long rate;
+ u8 mdiv;
+
+ regmap_read(vc3->regmap, pfd->offs, &prediv);
+ if (hwdata->num == VC3_PFD1) {
+ /* The bypass_prediv is set, PLL fed from Ref_in directly. */
+ if (prediv & pfd->mdiv1_bitmsk) {
+ /* check doubler is set or not */
+ regmap_read(vc3->regmap, VC3_PLL1_CTRL_OUTDIV5, &premul);
+ if (premul & VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER)
+ parent_rate *= 2;
+ return parent_rate;
+ }
+ mdiv = VC3_PLL1_M_DIV(prediv);
+ } else if (hwdata->num == VC3_PFD2) {
+ /* The bypass_prediv is set, PLL fed from Ref_in directly. */
+ if (prediv & pfd->mdiv1_bitmsk) {
+ /* check doubler is set or not */
+ if (premul & VC3_PLL2_MDIV_DOUBLER)
+ parent_rate *= 2;
+ return parent_rate;
+ }
+
+ mdiv = VC3_PLL2_M_DIV(prediv);
+ } else {
+ /* The bypass_prediv is set, PLL fed from Ref_in directly. */
+ if (prediv & pfd->mdiv1_bitmsk)
+ return parent_rate;
+
+ mdiv = VC3_PLL3_M_DIV(prediv);
+ }
+
+ if (prediv & pfd->mdiv2_bitmsk)
+ rate = parent_rate / 2;
+ else
+ rate = parent_rate / mdiv;
+
+ return rate;
+}
+
+static long vc3_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ unsigned long idiv;
+
+ /* PLL cannot operate with input clock above 50 MHz. */
+ if (rate > 50000000)
+ return -EINVAL;
+
+ /* CLKIN within range of PLL input, feed directly to PLL. */
+ if (*parent_rate <= 50000000)
+ return *parent_rate;
+
+ idiv = DIV_ROUND_UP(*parent_rate, rate);
+ if (hwdata->num == VC3_PFD1 || hwdata->num == VC3_PFD3) {
+ if (idiv > 63)
+ return -EINVAL;
+ } else {
+ if (idiv > 31)
+ return -EINVAL;
+ }
+
+ return *parent_rate / idiv;
+}
+
+static int vc3_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_pfd_data *pfd = hwdata->data;
+ struct vc3_driver_data *vc3 = hwdata->vc3;
+ unsigned long idiv;
+ u8 div;
+
+ /* CLKIN within range of PLL input, feed directly to PLL. */
+ if (parent_rate <= 50000000) {
+ regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk,
+ pfd->mdiv1_bitmsk);
+ regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk, 0);
+ return 0;
+ }
+
+ idiv = DIV_ROUND_UP(parent_rate, rate);
+ /* We have dedicated div-2 predivider. */
+ if (idiv == 2) {
+ regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk,
+ pfd->mdiv2_bitmsk);
+ regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk, 0);
+ } else {
+ if (hwdata->num == VC3_PFD1)
+ div = VC3_PLL1_M_DIV(idiv);
+ else if (hwdata->num == VC3_PFD2)
+ div = VC3_PLL2_M_DIV(idiv);
+ else
+ div = VC3_PLL3_M_DIV(idiv);
+
+ regmap_write(vc3->regmap, pfd->offs, div);
+ }
+
+ return 0;
+}
+
+static const struct clk_ops vc3_pfd_ops = {
+ .recalc_rate = vc3_pfd_recalc_rate,
+ .round_rate = vc3_pfd_round_rate,
+ .set_rate = vc3_pfd_set_rate,
+};
+
+static unsigned long vc3_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_pll_data *pll = hwdata->data;
+ struct vc3_driver_data *vc3 = hwdata->vc3;
+ u32 div_int, div_frc, val;
+ unsigned long rate;
+
+ regmap_read(vc3->regmap, pll->int_div_msb_offs, &val);
+ div_int = (val & GENMASK(2, 0)) << 8;
+ regmap_read(vc3->regmap, pll->int_div_lsb_offs, &val);
+ div_int |= val;
+
+ if (hwdata->num == VC3_PLL2) {
+ regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB, &val);
+ div_frc = val << 8;
+ regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB, &val);
+ div_frc |= val;
+ rate = (parent_rate *
+ (div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
+ } else {
+ rate = parent_rate * div_int;
+ }
+
+ return rate;
+}
+
+static long vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_pll_data *pll = hwdata->data;
+ u64 div_frc;
+
+ if (rate < pll->vco_min)
+ rate = pll->vco_min;
+ if (rate > pll->vco_max)
+ rate = pll->vco_max;
+
+ hwdata->div_int = rate / *parent_rate;
+
+ if (hwdata->num == VC3_PLL2) {
+ if (hwdata->div_int > 0x7ff)
+ rate = *parent_rate * 0x7ff;
+
+ /* Determine best fractional part, which is 16 bit wide */
+ div_frc = rate % *parent_rate;
+ div_frc *= BIT(16) - 1;
+ do_div(div_frc, *parent_rate);
+
+ hwdata->div_frc = (u32)div_frc;
+ rate = (*parent_rate *
+ (hwdata->div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
+ } else {
+ rate = *parent_rate * hwdata->div_int;
+ }
+
+ return rate;
+}
+
+static int vc3_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_pll_data *pll = hwdata->data;
+ struct vc3_driver_data *vc3 = hwdata->vc3;
+ u32 val;
+
+ regmap_read(vc3->regmap, pll->int_div_msb_offs, &val);
+ val = (val & 0xf8) | ((hwdata->div_int >> 8) & 0x7);
+ regmap_write(vc3->regmap, pll->int_div_msb_offs, val);
+ regmap_write(vc3->regmap, pll->int_div_lsb_offs, hwdata->div_int & 0xff);
+
+ if (hwdata->num == VC3_PLL2) {
+ regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB,
+ hwdata->div_frc >> 8);
+ regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB,
+ hwdata->div_frc & 0xff);
+ }
+
+ return 0;
+}
+
+static const struct clk_ops vc3_pll_ops = {
+ .recalc_rate = vc3_pll_recalc_rate,
+ .round_rate = vc3_pll_round_rate,
+ .set_rate = vc3_pll_set_rate,
+};
+
+static unsigned char vc3_div_mux_get_parent(struct clk_hw *hw)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_clk_data *div_mux = hwdata->data;
+ struct vc3_driver_data *vc3 = hwdata->vc3;
+ u32 src;
+
+ regmap_read(vc3->regmap, div_mux->offs, &src);
+
+ return !!(src & div_mux->bitmsk);
+}
+
+static int vc3_div_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_clk_data *div_mux = hwdata->data;
+ struct vc3_driver_data *vc3 = hwdata->vc3;
+
+ regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk,
+ index ? div_mux->bitmsk : 0);
+
+ return 0;
+}
+
+static const struct clk_ops vc3_div_mux_ops = {
+ .set_parent = vc3_div_mux_set_parent,
+ .get_parent = vc3_div_mux_get_parent,
+};
+
+static unsigned int vc3_get_div(const struct clk_div_table *table,
+ unsigned int val, unsigned long flag)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->val == val)
+ return clkt->div;
+
+ return 0;
+}
+
+static unsigned long vc3_div_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_div_data *div_data = hwdata->data;
+ struct vc3_driver_data *vc3 = hwdata->vc3;
+ unsigned int val;
+
+ regmap_read(vc3->regmap, div_data->offs, &val);
+ val >>= div_data->shift;
+ val &= VC3_DIV_MASK(div_data->width);
+
+ return divider_recalc_rate(hw, parent_rate, val, div_data->table,
+ hwdata->flags, div_data->width);
+}
+
+static long vc3_div_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_div_data *div_data = hwdata->data;
+ struct vc3_driver_data *vc3 = hwdata->vc3;
+ unsigned int bestdiv;
+
+ /* if read only, just return current value */
+ if (hwdata->flags & CLK_DIVIDER_READ_ONLY) {
+ regmap_read(vc3->regmap, div_data->offs, &bestdiv);
+ bestdiv >>= div_data->shift;
+ bestdiv &= VC3_DIV_MASK(div_data->width);
+ bestdiv = vc3_get_div(div_data->table, bestdiv, hwdata->flags);
+ return DIV_ROUND_UP(*parent_rate, bestdiv);
+ }
+
+ return divider_round_rate(hw, rate, parent_rate, div_data->table,
+ div_data->width, hwdata->flags);
+}
+
+static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_div_data *div_data = hwdata->data;
+ struct vc3_driver_data *vc3 = hwdata->vc3;
+ unsigned int value;
+
+ value = divider_get_val(rate, parent_rate, div_data->table,
+ div_data->width, hwdata->flags);
+ regmap_update_bits(vc3->regmap, div_data->offs,
+ VC3_DIV_MASK(div_data->width) << div_data->shift,
+ value << div_data->shift);
+ return 0;
+}
+
+static const struct clk_ops vc3_div_ops = {
+ .recalc_rate = vc3_div_recalc_rate,
+ .round_rate = vc3_div_round_rate,
+ .set_rate = vc3_div_set_rate,
+};
+
+static int vc3_clk_mux_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ int ret;
+ int frc;
+
+ ret = clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT);
+ if (ret) {
+ if (req->best_parent_rate / req->rate) {
+ frc = DIV_ROUND_CLOSEST_ULL(req->best_parent_rate,
+ req->rate);
+ req->rate *= frc;
+ return clk_mux_determine_rate_flags(hw, req,
+ CLK_SET_RATE_PARENT);
+ }
+ ret = 0;
+ }
+
+ return ret;
+}
+
+static unsigned char vc3_clk_mux_get_parent(struct clk_hw *hw)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_clk_data *clk_mux = hwdata->data;
+ struct vc3_driver_data *vc3 = hwdata->vc3;
+ u32 val;
+
+ regmap_read(vc3->regmap, clk_mux->offs, &val);
+
+ return !!(val & clk_mux->bitmsk);
+}
+
+static int vc3_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct vc3_hw_data *hwdata = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_clk_data *clk_mux = hwdata->data;
+ struct vc3_driver_data *vc3 = hwdata->vc3;
+
+ regmap_update_bits(vc3->regmap, clk_mux->offs,
+ clk_mux->bitmsk, index ? clk_mux->bitmsk : 0);
+ return 0;
+}
+
+static const struct clk_ops vc3_clk_mux_ops = {
+ .determine_rate = vc3_clk_mux_determine_rate,
+ .set_parent = vc3_clk_mux_set_parent,
+ .get_parent = vc3_clk_mux_get_parent,
+};
+
+static unsigned long vc3_clk_out_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return parent_rate;
+}
+
+static long vc3_clk_out_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ *prate = clk_hw_round_rate(clk_hw_get_parent(hw), rate);
+
+ return *prate;
+}
+
+static int vc3_clk_out_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ /*
+ * We must report success. round_rate() propagates rate to the
+ * parent and based on the rate mux changes its parent.
+ */
+
+ return 0;
+}
+
+const struct clk_ops vc3_clk_out_ops = {
+ .recalc_rate = vc3_clk_out_recalc_rate,
+ .round_rate = vc3_clk_out_round_rate,
+ .set_rate = vc3_clk_out_set_rate,
+};
+
+static bool vc3_regmap_is_writeable(struct device *dev, unsigned int reg)
+{
+ return true;
+}
+
+static const struct regmap_config vc3_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .cache_type = REGCACHE_RBTREE,
+ .max_register = 0x24,
+ .writeable_reg = vc3_regmap_is_writeable,
+};
+
+static struct clk_hw *vc3_of_clk_get(struct of_phandle_args *clkspec,
+ void *data)
+{
+ struct vc3_driver_data *vc3 = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= ARRAY_SIZE(clk_out_data)) {
+ pr_err("invalid clk index %u for provider %pOF\n", idx, clkspec->np);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return &vc3->clk_out[idx].hw;
+}
+
+static void vc3_divider_type_parse_dt(struct device *dev,
+ struct vc3_driver_data *vc3)
+{
+ struct device_node *np = dev->of_node;
+ struct property *prop;
+ const __be32 *p;
+ u32 i = 0;
+ u32 val;
+
+ of_property_for_each_u32(np, "assigned-clock-rates",
+ prop, p, val) {
+ if (i >= ARRAY_SIZE(div_data))
+ break;
+ if (val)
+ vc3->clk_div[i].flags = CLK_DIVIDER_READ_ONLY;
+
+ i++;
+ }
+}
+
+static void vc3_fill_init_data_parent(struct clk_init_data *init,
+ const struct vc3_clk_data *mux,
+ const struct clk_ops *ops,
+ const struct clk_parent_data *pdata,
+ int n)
+{
+ init->name = mux->name;
+ init->ops = ops;
+ init->flags = CLK_SET_RATE_PARENT;
+ init->parent_data = pdata;
+ init->num_parents = n;
+}
+
+static int vc3_clk_register(struct device *dev, struct vc3_driver_data *vc3,
+ struct vc3_hw_data *data, const void *clk_data,
+ const struct clk_init_data *init, int n)
+{
+ data->hw.init = init;
+ data->num = n;
+ data->vc3 = vc3;
+ data->data = clk_data;
+
+ return devm_clk_hw_register(dev, &data->hw);
+}
+
+static int vc3_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ u8 settings[NUM_CONFIG_REGISTERS];
+ struct vc3_driver_data *vc3;
+ struct clk_init_data init;
+ int ret, i;
+
+ vc3 = devm_kzalloc(dev, sizeof(*vc3), GFP_KERNEL);
+ if (!vc3)
+ return -ENOMEM;
+
+ i2c_set_clientdata(client, vc3);
+ vc3->client = client;
+
+ vc3->regmap = devm_regmap_init_i2c(client, &vc3_regmap_config);
+ if (IS_ERR(vc3->regmap))
+ return dev_err_probe(dev, PTR_ERR(vc3->regmap),
+ "failed to allocate register map\n");
+
+ ret = of_property_read_u8_array(dev->of_node, "renesas,settings",
+ settings, ARRAY_SIZE(settings));
+ if (!ret) {
+ /*
+ * A raw settings array was specified in the DT. Write the
+ * settings to the device immediately.
+ */
+ for (i = 0; i < NUM_CONFIG_REGISTERS; i++) {
+ ret = regmap_write(vc3->regmap, i, settings[i]);
+ if (ret) {
+ dev_err(dev, "error writing to chip (%i)\n", ret);
+ return ret;
+ }
+ }
+ } else if (ret == -EOVERFLOW) {
+ dev_err(&client->dev, "EOVERFLOW reg settings. ARRAY_SIZE: %zu",
+ ARRAY_SIZE(settings));
+ return ret;
+ }
+
+ /* Register clock ref */
+ memset(&init, 0, sizeof(init));
+
+ /* Register pfd muxes */
+ for (i = 0; i < ARRAY_SIZE(pfd_mux_data); i++) {
+ vc3_fill_init_data_parent(&init, &pfd_mux_data[i], &vc3_pfd_mux_ops,
+ pfdmux_p, ARRAY_SIZE(pfdmux_p));
+ ret = vc3_clk_register(dev, vc3, &vc3->clk_pfd_mux[i],
+ &pfd_mux_data[i], &init, i);
+ if (ret)
+ return dev_err_probe(dev, ret, "%s failed\n", init.name);
+ }
+
+ /* Register pfd's */
+ for (i = 0; i < ARRAY_SIZE(pfd_data); i++) {
+ init.name = pfd_data[i].name;
+ init.ops = &vc3_pfd_ops;
+ init.flags = CLK_SET_RATE_PARENT;
+ init.num_parents = 1;
+ init.parent_data = &pfd_p[i];
+
+ ret = vc3_clk_register(dev, vc3, &vc3->clk_pfd[i],
+ &pfd_data[i], &init, i);
+ if (ret)
+ return dev_err_probe(dev, ret, "%s failed\n", init.name);
+ }
+
+ /* Register pll's */
+ for (i = 0; i < ARRAY_SIZE(pll_data); i++) {
+ init.name = pll_data[i].name;
+ init.ops = &vc3_pll_ops;
+ init.flags = CLK_SET_RATE_PARENT;
+ init.num_parents = 1;
+ init.parent_data = &pll_p[i];
+
+ ret = vc3_clk_register(dev, vc3, &vc3->clk_pll[i],
+ &pll_data[i], &init, i);
+ if (ret)
+ return dev_err_probe(dev, ret, "%s failed\n", init.name);
+ }
+
+ /* Register divider muxes */
+ for (i = 0; i < ARRAY_SIZE(div_mux_data); i++) {
+ vc3_fill_init_data_parent(&init, &div_mux_data[i], &vc3_div_mux_ops,
+ divmux_p[i], 2);
+
+ ret = vc3_clk_register(dev, vc3, &vc3->clk_div_mux[i],
+ &div_mux_data[i], &init, i);
+ if (ret)
+ return dev_err_probe(dev, ret, "%s failed\n", init.name);
+ }
+
+ vc3_divider_type_parse_dt(dev, vc3);
+ /* Register dividers */
+ for (i = 0; i < ARRAY_SIZE(div_data); i++) {
+ init.name = div_data[i].name;
+ init.ops = &vc3_div_ops;
+ init.flags = CLK_SET_RATE_PARENT;
+ init.num_parents = 1;
+ init.parent_data = &div_p[i];
+
+ ret = vc3_clk_register(dev, vc3, &vc3->clk_div[i],
+ &div_data[i], &init, i);
+ if (ret)
+ return dev_err_probe(dev, ret, "%s failed\n", init.name);
+ }
+
+ /* Register clk muxes */
+ for (i = 0; i < ARRAY_SIZE(clk_mux_data); i++) {
+ vc3_fill_init_data_parent(&init, &clk_mux_data[i], &vc3_clk_mux_ops,
+ clkmux_p[i], 2);
+ ret = vc3_clk_register(dev, vc3, &vc3->clk_mux[i],
+ &clk_mux_data[i], &init, i);
+ if (ret)
+ return dev_err_probe(dev, ret, "%s failed\n", init.name);
+ }
+
+ /* Register clk outputs */
+ for (i = 0; i < ARRAY_SIZE(clk_out_data); i++) {
+ vc3_fill_init_data_parent(&init, &clk_out_data[i], &vc3_clk_out_ops,
+ &clkout_p[i], 1);
+ ret = vc3_clk_register(dev, vc3, &vc3->clk_out[i],
+ &clk_out_data[i], &init, i);
+ if (ret)
+ return dev_err_probe(dev, ret, "%s failed\n", init.name);
+ }
+
+ ret = devm_of_clk_add_hw_provider(dev, vc3_of_clk_get, vc3);
+ if (ret)
+ return dev_err_probe(dev, ret, "unable to add clk provider\n");
+
+ return ret;
+}
+
+static const struct of_device_id dev_ids[] = {
+ { .compatible = "renesas,5p35023" },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dev_ids);
+
+static struct i2c_driver vc3_driver = {
+ .driver = {
+ .name = "vc3",
+ .of_match_table = of_match_ptr(dev_ids),
+ },
+ .probe_new = vc3_probe,
+};
+module_i2c_driver(vc3_driver);
+
+MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas VersaClock 3 driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] arm64: dts: renesas: rzg2l-smarc: Use versa3 clk for audio mclk
2023-03-09 16:55 [PATCH v2 0/3] Add Versa3 clock generator support Biju Das
2023-03-09 16:55 ` [PATCH v2 1/3] dt-bindings: clock: Add Renesas versa3 clock generator bindings Biju Das
2023-03-09 16:55 ` [PATCH v2 2/3] drivers: clk: Add support for versa3 clock driver Biju Das
@ 2023-03-09 16:55 ` Biju Das
2 siblings, 0 replies; 9+ messages in thread
From: Biju Das @ 2023-03-09 16:55 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Prabhakar Mahadev Lad
Currently audio mclk uses a fixed clk 11.2896MHz(multiple of 44.1KHz).
Replace this fixed clk to programmable versa3 clk that can provide
2 rates 11.2896MHz and 12.2880(multiple of 48KHz) based on audio
sampling rate for the playback/record.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../boot/dts/renesas/rz-smarc-common.dtsi | 7 ----
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 32 +++++++++++++++++++
2 files changed, 32 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
index 3962d47b3e59..d724f49bd067 100644
--- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
@@ -32,12 +32,6 @@ chosen {
stdout-path = "serial0:115200n8";
};
- audio_mclock: audio_mclock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <11289600>;
- };
-
snd_rzg2l: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -55,7 +49,6 @@ cpu_dai: simple-audio-card,cpu {
};
codec_dai: simple-audio-card,codec {
- clocks = <&audio_mclock>;
sound-dai = <&wm8978>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index e180a955b6ac..4a84076cc85e 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -16,12 +16,22 @@ aliases {
serial1 = &scif2;
i2c3 = &i2c3;
};
+
+ x1_x2: xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
};
&cpu_dai {
sound-dai = <&ssi0>;
};
+&codec_dai {
+ clocks = <&versa3 3>;
+};
+
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
@@ -29,6 +39,28 @@ &i2c3 {
status = "okay";
+ versa3: versa3@68 {
+ compatible = "renesas,5p35023";
+ reg = <0x68>;
+ #clock-cells = <1>;
+ clocks = <&x1_x2>;
+
+ renesas,settings = [
+ 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
+ 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
+ 80 b0 45 c4 95
+ ];
+ assigned-clocks = <&versa3 0>,
+ <&versa3 1>,
+ <&versa3 2>,
+ <&versa3 3>,
+ <&versa3 4>,
+ <&versa3 5>;
+ assigned-clock-rates = <12288000>, <25000000>,
+ <12000000>, <11289600>,
+ <11289600>, <24000000>;
+ };
+
wm8978: codec@1a {
compatible = "wlf,wm8978";
#sound-dai-cells = <0>;
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: clock: Add Renesas versa3 clock generator bindings
2023-03-09 16:55 ` [PATCH v2 1/3] dt-bindings: clock: Add Renesas versa3 clock generator bindings Biju Das
@ 2023-03-10 8:47 ` Krzysztof Kozlowski
2023-03-10 9:02 ` Biju Das
0 siblings, 1 reply; 9+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-10 8:47 UTC (permalink / raw)
To: Biju Das, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski
Cc: Geert Uytterhoeven, linux-renesas-soc, linux-clk, devicetree,
Prabhakar Mahadev Lad
On 09/03/2023 17:55, Biju Das wrote:
> Document Renesas versa3 clock generator(5P35023) bindings.
>
> The 5P35023 is a VersaClock programmable clock generator and
> is designed for low-power, consumer, and high-performance PCI
> Express applications. The 5P35023 device is a three PLL
> architecture design, and each PLL is individually programmable
> and allowing for up to 6 unique frequency outputs.
>
Thank you for your patch. There is something to discuss/improve.
> +description: |
> + The 5P35023 is a VersaClock programmable clock generator and
> + is designed for low-power, consumer, and high-performance PCI
> + express applications. The 5P35023 device is a three PLL
> + architecture design, and each PLL is individually programmable
> + and allowing for up to 6 unique frequency outputs.
> +
> + An internal OTP memory allows the user to store the configuration
> + in the device. After power up, the user can change the device register
> + settings through the I2C interface when I2C mode is selected.
> +
> + The driver can read a full register map from the DT, and will use that
> + register map to initialize the attached part (via I2C) when the system
> + boots. Any configuration not supported by the common clock framework
> + must be done via the full register map, including optimized settings.
> +
> + Link to datasheet: |
| is not correct here
> + https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator
> +
> +properties:
> + compatible:
> + enum:
> + - renesas,5p35023
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> + clocks:
> + maxItems: 1
> +
> + renesas,settings:
> + description: Optional, complete register map of the device.
> + Optimized settings for the device must be provided in full
> + and are written during initialization.
> + $ref: /schemas/types.yaml#/definitions/uint8-array
> + maxItems: 37
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
Stray blank line, drop.
> + i2c {
> + #address-cells = <1>;
> + #size-cells = <0>;
With both above:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v2 1/3] dt-bindings: clock: Add Renesas versa3 clock generator bindings
2023-03-10 8:47 ` Krzysztof Kozlowski
@ 2023-03-10 9:02 ` Biju Das
0 siblings, 0 replies; 9+ messages in thread
From: Biju Das @ 2023-03-10 9:02 UTC (permalink / raw)
To: Krzysztof Kozlowski, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski
Cc: Geert Uytterhoeven, linux-renesas-soc, linux-clk, devicetree,
Prabhakar Mahadev Lad
Hi Krzysztof Kozlowski,
Thanks for the feedback.
> Subject: Re: [PATCH v2 1/3] dt-bindings: clock: Add Renesas versa3 clock
> generator bindings
>
> On 09/03/2023 17:55, Biju Das wrote:
> > Document Renesas versa3 clock generator(5P35023) bindings.
> >
> > The 5P35023 is a VersaClock programmable clock generator and is
> > designed for low-power, consumer, and high-performance PCI Express
> > applications. The 5P35023 device is a three PLL architecture design,
> > and each PLL is individually programmable and allowing for up to 6
> > unique frequency outputs.
> >
>
> Thank you for your patch. There is something to discuss/improve.
>
> > +description: |
> > + The 5P35023 is a VersaClock programmable clock generator and
> > + is designed for low-power, consumer, and high-performance PCI
> > + express applications. The 5P35023 device is a three PLL
> > + architecture design, and each PLL is individually programmable
> > + and allowing for up to 6 unique frequency outputs.
> > +
> > + An internal OTP memory allows the user to store the configuration
> > + in the device. After power up, the user can change the device
> > + register settings through the I2C interface when I2C mode is selected.
> > +
> > + The driver can read a full register map from the DT, and will use
> > + that register map to initialize the attached part (via I2C) when
> > + the system boots. Any configuration not supported by the common
> > + clock framework must be done via the full register map, including
> optimized settings.
> > +
> > + Link to datasheet: |
>
> | is not correct here
OK will remove.
>
> > +
> > + https://www.renesas.com/us/en/products/clocks-timing/clock-generatio
> > + n/programmable-clocks/5p35023-versaclock-3s-programmable-clock-gener
> > + ator
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - renesas,5p35023
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + '#clock-cells':
> > + const: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + renesas,settings:
> > + description: Optional, complete register map of the device.
> > + Optimized settings for the device must be provided in full
> > + and are written during initialization.
> > + $ref: /schemas/types.yaml#/definitions/uint8-array
> > + maxItems: 37
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - '#clock-cells'
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
>
> Stray blank line, drop.
Agreed. Will send next version based on feedback for the driver patch and reviews
from others.
Cheers,
Biju
>
> > + i2c {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> With both above:
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/3] drivers: clk: Add support for versa3 clock driver
2023-03-09 16:55 ` [PATCH v2 2/3] drivers: clk: Add support for versa3 clock driver Biju Das
@ 2023-03-21 23:16 ` Stephen Boyd
2023-03-24 7:56 ` Biju Das
0 siblings, 1 reply; 9+ messages in thread
From: Stephen Boyd @ 2023-03-21 23:16 UTC (permalink / raw)
To: Biju Das, Michael Turquette
Cc: Biju Das, linux-clk, Geert Uytterhoeven, Prabhakar Mahadev Lad,
linux-renesas-soc
Quoting Biju Das (2023-03-09 08:55:28)
> diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c
> new file mode 100644
> index 000000000000..6c5c8b37f6af
> --- /dev/null
> +++ b/drivers/clk/clk-versaclock3.c
> @@ -0,0 +1,1139 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Driver for Renesas Versaclock 3
> + *
> + * Copyright (C) 2021 Renesas Electronics Corp.
> + */
> +
[...]
> + [vc3_se1] = "se1",
> + [vc3_ref] = "ref"
> +};
> +
> +static const struct clk_parent_data pfdmux_p[] = {
> + { .fw_name = vc3_fin_name, .name = vc3_fin_name },
New drivers should only have .fw_name here. I don't think you're
migrating an existing driver to clk_parent_data so .name should be
removed. And then maybe you'll want to simply use the index instead so
that we don't have to do any string comparisons to find clk parents.
> + { .fw_name = "div2", .name = "div2" }
> +};
> +
[...]
> +
> +static unsigned long vc3_clk_out_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + return parent_rate;
> +}
> +
> +static long vc3_clk_out_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate)
> +{
> + *prate = clk_hw_round_rate(clk_hw_get_parent(hw), rate);
> +
> + return *prate;
> +}
> +
> +static int vc3_clk_out_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + /*
> + * We must report success. round_rate() propagates rate to the
> + * parent and based on the rate mux changes its parent.
> + */
> +
> + return 0;
> +}
> +
> +const struct clk_ops vc3_clk_out_ops = {
> + .recalc_rate = vc3_clk_out_recalc_rate,
> + .round_rate = vc3_clk_out_round_rate,
> + .set_rate = vc3_clk_out_set_rate,
> +};
Are any of these clk ops necessary? They don't do anything besides pass
up to the parent, so you can set CLK_SET_RATE_PARENT and be done?
> +
> +static bool vc3_regmap_is_writeable(struct device *dev, unsigned int reg)
> +{
> + return true;
> +}
> +
> +static const struct regmap_config vc3_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 8,
> + .cache_type = REGCACHE_RBTREE,
> + .max_register = 0x24,
> + .writeable_reg = vc3_regmap_is_writeable,
> +};
> +
> +static struct clk_hw *vc3_of_clk_get(struct of_phandle_args *clkspec,
> + void *data)
> +{
> + struct vc3_driver_data *vc3 = data;
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx >= ARRAY_SIZE(clk_out_data)) {
> + pr_err("invalid clk index %u for provider %pOF\n", idx, clkspec->np);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + return &vc3->clk_out[idx].hw;
> +}
> +
> +static void vc3_divider_type_parse_dt(struct device *dev,
> + struct vc3_driver_data *vc3)
> +{
> + struct device_node *np = dev->of_node;
> + struct property *prop;
> + const __be32 *p;
> + u32 i = 0;
> + u32 val;
> +
> + of_property_for_each_u32(np, "assigned-clock-rates",
This is an interesting use of assigned-clock-rates.
> + prop, p, val) {
> + if (i >= ARRAY_SIZE(div_data))
> + break;
> + if (val)
> + vc3->clk_div[i].flags = CLK_DIVIDER_READ_ONLY;
Why would assigned clock rates change the read only flag?
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v2 2/3] drivers: clk: Add support for versa3 clock driver
2023-03-21 23:16 ` Stephen Boyd
@ 2023-03-24 7:56 ` Biju Das
[not found] ` <b8e22286a7d1995f2e74c4dd3fec88a8.sboyd@kernel.org>
0 siblings, 1 reply; 9+ messages in thread
From: Biju Das @ 2023-03-24 7:56 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: linux-clk, Geert Uytterhoeven, Prabhakar Mahadev Lad,
linux-renesas-soc, Krzysztof Kozlowski, Rob Herring
Hi Stephen,
Thanks for the feedback.
> -----Original Message-----
> From: Stephen Boyd <sboyd@kernel.org>
> Sent: Tuesday, March 21, 2023 11:16 PM
> To: Biju Das <biju.das.jz@bp.renesas.com>; Michael Turquette
> <mturquette@baylibre.com>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>; linux-clk@vger.kernel.org; Geert
> Uytterhoeven <geert+renesas@glider.be>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>; linux-renesas-soc@vger.kernel.org
> Subject: Re: [PATCH v2 2/3] drivers: clk: Add support for versa3 clock
> driver
>
> Quoting Biju Das (2023-03-09 08:55:28)
> > diff --git a/drivers/clk/clk-versaclock3.c
> > b/drivers/clk/clk-versaclock3.c new file mode 100644 index
> > 000000000000..6c5c8b37f6af
> > --- /dev/null
> > +++ b/drivers/clk/clk-versaclock3.c
> > @@ -0,0 +1,1139 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Driver for Renesas Versaclock 3
> > + *
> > + * Copyright (C) 2021 Renesas Electronics Corp.
> > + */
> > +
> [...]
> > + [vc3_se1] = "se1",
> > + [vc3_ref] = "ref"
> > +};
> > +
> > +static const struct clk_parent_data pfdmux_p[] = {
> > + { .fw_name = vc3_fin_name, .name = vc3_fin_name },
>
> New drivers should only have .fw_name here. I don't think you're migrating
> an existing driver to clk_parent_data so .name should be removed. And then
> maybe you'll want to simply use the index instead so that we don't have to
> do any string comparisons to find clk parents.
+ Rob and Krzysztof Kozlowski
Agreed. But it requires the below change in device tree.
+ clock-names = "xtal";
Otherwise with just[1], devm_clk_hw_register is not assigning xtal as
Parent clock.
[1]
static const struct clk_parent_data pfdmux_p[] = {
{ .fw_name = "xtal"},
..
}
So I will update the bindings.
>
> > + { .fw_name = "div2", .name = "div2" } };
> > +
> [...]
> > +
> > +static unsigned long vc3_clk_out_recalc_rate(struct clk_hw *hw,
> > + unsigned long
> > +parent_rate) {
> > + return parent_rate;
> > +}
> > +
> > +static long vc3_clk_out_round_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long *prate) {
> > + *prate = clk_hw_round_rate(clk_hw_get_parent(hw), rate);
> > +
> > + return *prate;
> > +}
> > +
> > +static int vc3_clk_out_set_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long parent_rate) {
> > + /*
> > + * We must report success. round_rate() propagates rate to the
> > + * parent and based on the rate mux changes its parent.
> > + */
> > +
> > + return 0;
> > +}
> > +
> > +const struct clk_ops vc3_clk_out_ops = {
> > + .recalc_rate = vc3_clk_out_recalc_rate,
> > + .round_rate = vc3_clk_out_round_rate,
> > + .set_rate = vc3_clk_out_set_rate, };
>
> Are any of these clk ops necessary? They don't do anything besides pass up
> to the parent, so you can set CLK_SET_RATE_PARENT and be done?
Yes it is required, otherwise, I get Warn message [2] and it fails to register the clk hw.
[2] https://elixir.bootlin.com/linux/latest/source/drivers/clk/clk.c#L4120
>
> > +
> > +static bool vc3_regmap_is_writeable(struct device *dev, unsigned int
> > +reg) {
> > + return true;
> > +}
> > +
> > +static const struct regmap_config vc3_regmap_config = {
> > + .reg_bits = 8,
> > + .val_bits = 8,
> > + .cache_type = REGCACHE_RBTREE,
> > + .max_register = 0x24,
> > + .writeable_reg = vc3_regmap_is_writeable, };
> > +
> > +static struct clk_hw *vc3_of_clk_get(struct of_phandle_args *clkspec,
> > + void *data) {
> > + struct vc3_driver_data *vc3 = data;
> > + unsigned int idx = clkspec->args[0];
> > +
> > + if (idx >= ARRAY_SIZE(clk_out_data)) {
> > + pr_err("invalid clk index %u for provider %pOF\n", idx,
> clkspec->np);
> > + return ERR_PTR(-EINVAL);
> > + }
> > +
> > + return &vc3->clk_out[idx].hw;
> > +}
> > +
> > +static void vc3_divider_type_parse_dt(struct device *dev,
> > + struct vc3_driver_data *vc3) {
> > + struct device_node *np = dev->of_node;
> > + struct property *prop;
> > + const __be32 *p;
> > + u32 i = 0;
> > + u32 val;
> > +
> > + of_property_for_each_u32(np, "assigned-clock-rates",
>
> This is an interesting use of assigned-clock-rates.
>
> > + prop, p, val) {
> > + if (i >= ARRAY_SIZE(div_data))
> > + break;
> > + if (val)
> > + vc3->clk_div[i].flags = CLK_DIVIDER_READ_ONLY;
>
> Why would assigned clock rates change the read only flag?
I do not want to change the divider settings, so I thought of using
these properties to assign the read only flag to clock-divider flag.
I will remove this function in next version and Will use CLK_DIVIDER_READ_ONLY
flags for dividers.
Cheers,
Biju
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v2 2/3] drivers: clk: Add support for versa3 clock driver
[not found] ` <bc175ee5522d2d48ccef8b192c2a08d7.sboyd@kernel.org>
@ 2023-03-30 7:31 ` Biju Das
0 siblings, 0 replies; 9+ messages in thread
From: Biju Das @ 2023-03-30 7:31 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: Geert Uytterhoeven, Prabhakar Mahadev Lad, Krzysztof Kozlowski,
Rob Herring, linux-renesas-soc, linux-clk
Hi Stephen,
Thanks for the feedback.
> Subject: RE: [PATCH v2 2/3] drivers: clk: Add support for versa3 clock
> driver
>
> Quoting Biju Das (2023-03-28 11:07:59)
> >
> > Stream parameters are [ 35.051544] ###### vc3_clk_out_round_rate
> rate=12288000
> > 48000Hz, S16_LE,[ 35.051590] ###### vc3_clk_out_round_rate rate=12288000
> > 2 channels
> > Using 16 oc[ 35.058206] ###### vc3_clk_out_recalc_rate
> parent_rate=12287998
> > taves of pink noise
> > Rate set to 48000Hz (requested 48000Hz)
> >
> > Note:
> > I have tried taking out clk_ops and replaced below calls in
> > vc3_of_clk_get(),
> >
> > The clk mux doesn't get callbacks during playback to change the rates.
> >
> > if (idx == VC3_REF)
> > hw = devm_clk_hw_register_fixed_factor(dev, name, "xtal",
> >
> CLK_SET_RATE_PARENT, 1, 1);
> > else
> > hw = devm_clk_hw_register_fixed_factor_parent_hw(dev,
> name, &clk_mux[idx].hw,
> >
> > CLK_SET_RATE_PARENT, 1, 1);
>
> Does the clk that is a child of the fixed factor 1/1 clk also have
> CLK_SET_RATE_PARENT flag set?
There is no child for fixed factor 1/1 clk. I just dropped clk-fops and
Used fixed factor 1/1 for output clks and all parents of the output clks is
have CLK_SET_RATE_PARENT flag set.
diff2-mux is parent of fixed factor 1/1 "diff2" output clk
diff1-mux is parent of fixed factor 1/1 "diff1" output clk
se3-mux is parent of fixed factor 1/1 "se3" output clk
se2-mux is parent of fixed factor 1/1 "se2" output clk
se1-mux is parent of fixed factor 1/1 "se1" output clk
xtal is parent of fixed factor 1/1 "ref" output clk
static struct vc3_hw_data clk_mux[] = {
[VC3_DIFF2_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_DIFF2_CTRL_REG,
.bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL
},
.hw.init = &(struct clk_init_data){
.name = "diff2_mux",
.ops = &vc3_clk_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&clk_div[VC3_DIV1].hw,
&clk_div[VC3_DIV3].hw
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
},
[VC3_DIFF1_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_DIFF1_CTRL_REG,
.bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL
},
.hw.init = &(struct clk_init_data){
.name = "diff1_mux",
.ops = &vc3_clk_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&clk_div[VC3_DIV1].hw,
&clk_div[VC3_DIV3].hw
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
},
[VC3_SE3_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_SE3_DIFF1_CTRL_REG,
.bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL
},
.hw.init = &(struct clk_init_data){
.name = "se3_mux",
.ops = &vc3_clk_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&clk_div[VC3_DIV2].hw,
&clk_div[VC3_DIV4].hw
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
},
[VC3_SE2_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_SE2_CTRL_REG0,
.bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL
},
.hw.init = &(struct clk_init_data){
.name = "se2_mux",
.ops = &vc3_clk_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&clk_div[VC3_DIV5].hw,
&clk_div[VC3_DIV4].hw
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
},
[VC3_SE1_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_SE1_DIV4_CTRL,
.bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL
},
.hw.init = &(struct clk_init_data){
.name = "se1_mux",
.ops = &vc3_clk_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&clk_div[VC3_DIV5].hw,
&clk_div[VC3_DIV4].hw
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
}
};
xtal 0 0 0 24000000 0 0 50000 Y
ref 0 0 0 24000000 0 0 50000 Y
pfd1 0 0 0 24000000 0 0 50000 Y
pll1 0 0 0 600000000 0 0 50000 Y
div2 0 0 0 12000000 0 0 50000 Y
se3_mux 0 0 0 12000000 0 0 50000 Y
se3 0 0 0 12000000 0 0 50000 Y
div1_mux 0 0 0 600000000 0 0 50000 Y
div1 0 0 0 25000000 0 0 50000 Y
diff1_mux 0 0 0 25000000 0 0 50000 Y
diff1 0 0 0 25000000 0 0 50000 Y
pfd3_mux 0 0 0 24000000 0 0 50000 Y
pfd3 0 0 0 960000 0 0 50000 Y
pll3 0 0 0 564480000 0 0 50000 Y
div5 0 0 0 11289600 0 0 50000 Y
se1_mux 0 0 0 11289600 0 0 50000 Y
se1 0 0 0 11289600 0 0 50000 Y
se2_mux 0 0 0 11289600 0 0 50000 Y
se2 0 0 0 11289600 0 0 50000 Y
pfd2_mux 0 0 0 24000000 0 0 50000 Y
pfd2 0 0 0 24000000 0 0 50000 Y
pll2 0 0 0 491519897 0 0 50000 Y
div4_mux 0 0 0 491519897 0 0 50000 Y
div4 0 0 0 12287998 0 0 50000 Y
div3_mux 0 0 0 491519897 0 0 50000 Y
div3 0 0 0 12287998 0 0 50000 Y
diff2_mux 0 0 0 12287998 0 0 50000 Y
diff2 0 0 0 12287998 0 0 50000 Y
Cheers,
Biju
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-03-30 7:31 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-09 16:55 [PATCH v2 0/3] Add Versa3 clock generator support Biju Das
2023-03-09 16:55 ` [PATCH v2 1/3] dt-bindings: clock: Add Renesas versa3 clock generator bindings Biju Das
2023-03-10 8:47 ` Krzysztof Kozlowski
2023-03-10 9:02 ` Biju Das
2023-03-09 16:55 ` [PATCH v2 2/3] drivers: clk: Add support for versa3 clock driver Biju Das
2023-03-21 23:16 ` Stephen Boyd
2023-03-24 7:56 ` Biju Das
[not found] ` <b8e22286a7d1995f2e74c4dd3fec88a8.sboyd@kernel.org>
[not found] ` <OS0PR01MB592215D4433973416B550BA086889@OS0PR01MB5922.jpnprd01.prod.outlook.com>
[not found] ` <bc175ee5522d2d48ccef8b192c2a08d7.sboyd@kernel.org>
2023-03-30 7:31 ` Biju Das
2023-03-09 16:55 ` [PATCH v2 3/3] arm64: dts: renesas: rzg2l-smarc: Use versa3 clk for audio mclk Biju Das
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