From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v2 1/3] dt-bindings: clock: Add Renesas versa3 clock generator bindings
Date: Thu, 9 Mar 2023 16:55:27 +0000 [thread overview]
Message-ID: <20230309165529.223052-2-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20230309165529.223052-1-biju.das.jz@bp.renesas.com>
Document Renesas versa3 clock generator(5P35023) bindings.
The 5P35023 is a VersaClock programmable clock generator and
is designed for low-power, consumer, and high-performance PCI
Express applications. The 5P35023 device is a three PLL
architecture design, and each PLL is individually programmable
and allowing for up to 6 unique frequency outputs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
RFC->v2:
* Renamed the filename to match with compatible
* Added maintainers entry after title
* Removed the wrapping for the link to data sheet.
* Removed reg description
* Removed clock names
* Replaced minItems->maxItems in renesas,settings property
* Dropped assigned-clocks, assigned-clock-rates
* Dropped renesas,clock-divider-read-only and renesas,clock-flags
* Drooped clock handle part from example
* Dropped reg from example.
* Dropped consumer example
---
.../bindings/clock/renesas,5p35023.yaml | 90 +++++++++++++++++++
1 file changed, 90 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
new file mode 100644
index 000000000000..ee4afc2ea67b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ The 5P35023 is a VersaClock programmable clock generator and
+ is designed for low-power, consumer, and high-performance PCI
+ express applications. The 5P35023 device is a three PLL
+ architecture design, and each PLL is individually programmable
+ and allowing for up to 6 unique frequency outputs.
+
+ An internal OTP memory allows the user to store the configuration
+ in the device. After power up, the user can change the device register
+ settings through the I2C interface when I2C mode is selected.
+
+ The driver can read a full register map from the DT, and will use that
+ register map to initialize the attached part (via I2C) when the system
+ boots. Any configuration not supported by the common clock framework
+ must be done via the full register map, including optimized settings.
+
+ Link to datasheet: |
+ https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator
+
+properties:
+ compatible:
+ enum:
+ - renesas,5p35023
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ renesas,settings:
+ description: Optional, complete register map of the device.
+ Optimized settings for the device must be provided in full
+ and are written during initialization.
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+ maxItems: 37
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ versa3: clock-generator@68 {
+ compatible = "renesas,5p35023";
+ reg = <0x68>;
+ #clock-cells = <1>;
+
+ clocks = <&x1_x2>;
+
+ renesas,settings = [
+ 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
+ 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
+ 80 b0 45 c4 95
+ ];
+
+ assigned-clocks = <&versa3 0>,
+ <&versa3 1>,
+ <&versa3 2>,
+ <&versa3 3>,
+ <&versa3 4>,
+ <&versa3 5>;
+ assigned-clock-rates = <12288000>, <25000000>,
+ <12000000>, <11289600>,
+ <11289600>, <24000000>;
+ };
+ };
--
2.25.1
next prev parent reply other threads:[~2023-03-09 17:01 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-09 16:55 [PATCH v2 0/3] Add Versa3 clock generator support Biju Das
2023-03-09 16:55 ` Biju Das [this message]
2023-03-10 8:47 ` [PATCH v2 1/3] dt-bindings: clock: Add Renesas versa3 clock generator bindings Krzysztof Kozlowski
2023-03-10 9:02 ` Biju Das
2023-03-09 16:55 ` [PATCH v2 2/3] drivers: clk: Add support for versa3 clock driver Biju Das
2023-03-21 23:16 ` Stephen Boyd
2023-03-24 7:56 ` Biju Das
[not found] ` <b8e22286a7d1995f2e74c4dd3fec88a8.sboyd@kernel.org>
[not found] ` <OS0PR01MB592215D4433973416B550BA086889@OS0PR01MB5922.jpnprd01.prod.outlook.com>
[not found] ` <bc175ee5522d2d48ccef8b192c2a08d7.sboyd@kernel.org>
2023-03-30 7:31 ` Biju Das
2023-03-09 16:55 ` [PATCH v2 3/3] arm64: dts: renesas: rzg2l-smarc: Use versa3 clk for audio mclk Biju Das
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