* [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs
@ 2019-12-13 8:47 Lad Prabhakar
2019-12-13 8:47 ` [v2 1/6] pci: pcie-rcar: preparation for adding endpoint support Lad Prabhakar
` (6 more replies)
0 siblings, 7 replies; 27+ messages in thread
From: Lad Prabhakar @ 2019-12-13 8:47 UTC (permalink / raw)
To: Bjorn Helgaas, Rob Herring, Mark Rutland, Geert Uytterhoeven,
Magnus Damm, Kishon Vijay Abraham I, Marek Vasut,
Yoshihiro Shimoda, linux-pci
Cc: Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann,
Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel,
linux-arm-kernel, linux-renesas-soc, Chris Paterson,
Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman,
Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad,
Prabhakar
From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>
This patch series adds support for PCIe controller on rcar to work in endpoint mode,
this also extends the epf framework to handle features of outbound regions.
Note:
The cadence/rockchip/designware endpoint drivers are build tested only.
Changes for v2:
1] Fixed review comments from Biju for dt-bindings to include an example
for a tested platform.
2] Fixed review comments from Kishon to extend the features of outbound
regions in epf framework.
3] Added support to parse outbound-ranges in OF.
lspci output on host:
====================
01:00.0 Unassigned class [ff00]: Renesas Technology Corp. Device 002d
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin A routed to IRQ 152
Region 0: Memory at fe200200 (64-bit, non-prefetchable) [size=128]
Region 2: Memory at fe200000 (64-bit, non-prefetchable) [size=256]
Region 4: Memory at fe200100 (64-bit, non-prefetchable) [size=256]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
Address: 00000004fa36f000 Data: 0001
Masking: fffffffe Pending: 00000000
Capabilities: [70] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 128 bytes
DevSta: CorrErr+ UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend-
LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR-, OBFF Not Supported
AtomicOpsCap: 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
AtomicOpsCtl: ReqEn-
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [100 v1] Virtual Channel
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
Arb: Fixed- WRR32- WRR64- WRR128-
Ctrl: ArbSelect=Fixed
Status: InProgress-
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
Status: NegoPending- InProgress-
Kernel driver in use: pci-endpoint-test
00: 12 19 2d 00 06 00 10 00 00 00 00 ff 00 00 00 00
10: 04 02 20 fe 00 00 00 00 04 00 20 fe 00 00 00 00
20: 04 01 20 fe 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 98 01 00 00
BAR Test
========
root@g2e:~# pcitest -b 0
BAR0: OKAY
root@g2e:~# pcitest -b 1
BAR1: NOT OKAY
root@g2e:~# pcitest -b 2
BAR2: OKAY
root@g2e:~# pcitest -b 3
BAR3: NOT OKAY
root@g2e:~# pcitest -b 4
BAR4: OKAY
root@g2e:~# pcitest -b 5
BAR5: NOT OKAY
Note: BAR test for 1/3/5 fail because they are configured to be 64bits
Interrupt Test
==============
root@g2e:~# pcitest -i 0
SET IRQ TYPE TO LEGACY: OKAY
root@g2e:~# pcitest -l
LEGACY IRQ: OKAY
Read Test
=========
root@g2e:~# pcitest -r -s 1
READ ( 1 bytes): OKAY
root@g2e:~# pcitest -r -s 1024
READ ( 1024 bytes): OKAY
root@g2e:~# pcitest -r -s 1025
READ ( 1025 bytes): OKAY
root@g2e:~# pcitest -r -s 1024000
READ (1024000 bytes): OKAY
root@g2e:~# pcitest -r -s 1024001
READ (1024001 bytes): OKAY
Write Test
==========
root@g2e:~# pcitest -w -s 1
WRITE ( 1 bytes): OKAY
root@g2e:~# pcitest -w -s 1024
WRITE ( 1024 bytes): OKAY
root@g2e:~# pcitest -w -s 1025
WRITE ( 1025 bytes): OKAY
root@g2e:~# pcitest -w -s 1024000
WRITE (1024000 bytes): OKAY
root@g2e:~# pcitest -w -s 1024001
WRITE (1024001 bytes): OKAY
Copy Test
=========
root@g2e:~# pcitest -c -s 1
COPY ( 1 bytes): OKAY
root@g2e:~# pcitest -c -s 1024
COPY ( 1024 bytes): OKAY
root@g2e:~# pcitest -c -s 1025
COPY ( 1025 bytes): OKAY
root@g2e:~# pcitest -c -s 1024000
COPY (1024000 bytes): OKAY
root@g2e:~# pcitest -c -s 1024001
COPY (1024001 bytes): OKAY
Lad, Prabhakar (6):
pci: pcie-rcar: preparation for adding endpoint support
pci: endpoint: add support to handle features of outbound memory
of: address: add support to parse PCI outbound-ranges
dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint
controller
pci: rcar: add support for rcar pcie controller in endpoint mode
misc: pci_endpoint_test: add device-id for RZ/G2E pcie controller
.../devicetree/bindings/pci/rcar-pci-ep.txt | 37 +
arch/arm64/configs/defconfig | 2 +-
drivers/misc/pci_endpoint_test.c | 3 +
drivers/of/address.c | 44 +-
drivers/pci/controller/Kconfig | 11 +-
drivers/pci/controller/Makefile | 3 +-
drivers/pci/controller/dwc/pcie-designware-ep.c | 30 +-
drivers/pci/controller/pcie-cadence-ep.c | 11 +-
drivers/pci/controller/pcie-rcar-ep.c | 494 ++++++++
drivers/pci/controller/pcie-rcar-host.c | 1056 +++++++++++++++++
drivers/pci/controller/pcie-rcar.c | 1229 +-------------------
drivers/pci/controller/pcie-rcar.h | 129 ++
drivers/pci/controller/pcie-rockchip-ep.c | 13 +-
drivers/pci/endpoint/functions/pci-epf-test.c | 47 +-
drivers/pci/endpoint/pci-epc-core.c | 7 +-
drivers/pci/endpoint/pci-epc-mem.c | 216 +++-
include/linux/of_address.h | 21 +
include/linux/pci-epc.h | 72 +-
18 files changed, 2152 insertions(+), 1273 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/rcar-pci-ep.txt
create mode 100644 drivers/pci/controller/pcie-rcar-ep.c
create mode 100644 drivers/pci/controller/pcie-rcar-host.c
create mode 100644 drivers/pci/controller/pcie-rcar.h
--
2.7.4
^ permalink raw reply [flat|nested] 27+ messages in thread* [v2 1/6] pci: pcie-rcar: preparation for adding endpoint support 2019-12-13 8:47 [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs Lad Prabhakar @ 2019-12-13 8:47 ` Lad Prabhakar 2019-12-13 21:06 ` Bjorn Helgaas 2019-12-13 8:47 ` [v2 2/6] pci: endpoint: add support to handle features of outbound memory Lad Prabhakar ` (5 subsequent siblings) 6 siblings, 1 reply; 27+ messages in thread From: Lad Prabhakar @ 2019-12-13 8:47 UTC (permalink / raw) To: Bjorn Helgaas, Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci Cc: Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel, linux-arm-kernel, linux-renesas-soc, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> this patch prepares for adding endpoint support to rcar controller, there are no functional changes with this patch, a common file is created so that it can be shared with endpoint driver. Alongside this patch fixes checkpatch reported issues. Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/configs/defconfig | 2 +- drivers/pci/controller/Kconfig | 4 +- drivers/pci/controller/Makefile | 2 +- drivers/pci/controller/pcie-rcar-host.c | 1056 ++++++++++++++++++++++++++ drivers/pci/controller/pcie-rcar.c | 1229 ++----------------------------- drivers/pci/controller/pcie-rcar.h | 129 ++++ 6 files changed, 1242 insertions(+), 1180 deletions(-) create mode 100644 drivers/pci/controller/pcie-rcar-host.c create mode 100644 drivers/pci/controller/pcie-rcar.h diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c9a867a..42e2cd8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -182,7 +182,7 @@ CONFIG_HOTPLUG_PCI=y CONFIG_HOTPLUG_PCI_ACPI=y CONFIG_PCI_AARDVARK=y CONFIG_PCI_TEGRA=y -CONFIG_PCIE_RCAR=y +CONFIG_PCIE_RCAR_HOST=y CONFIG_PCI_HOST_GENERIC=y CONFIG_PCI_XGENE=y CONFIG_PCIE_ALTERA=y diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index b176b2f..d3b82f7 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -82,12 +82,12 @@ config PCI_RCAR_GEN2 There are 3 internal PCI controllers available with a single built-in EHCI/OHCI host controller present on each one. -config PCIE_RCAR +config PCIE_RCAR_HOST bool "Renesas R-Car PCIe controller" depends on ARCH_RENESAS || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN help - Say Y here if you want PCIe controller support on R-Car SoCs. + Say Y here if you want PCIe controller support on R-Car SoCs in host mode. config PCI_HOST_COMMON bool diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index a2a22c9..3577902 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o -obj-$(CONFIG_PCIE_RCAR) += pcie-rcar.o +obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o obj-$(CONFIG_PCI_HOST_COMMON) += pci-host-common.o obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o diff --git a/drivers/pci/controller/pcie-rcar-host.c b/drivers/pci/controller/pcie-rcar-host.c new file mode 100644 index 0000000..8b432ce --- /dev/null +++ b/drivers/pci/controller/pcie-rcar-host.c @@ -0,0 +1,1056 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe driver for Renesas R-Car SoCs + * Copyright (C) 2014-2019 Renesas Electronics Europe Ltd + * + * Based on: + * arch/sh/drivers/pci/pcie-sh7786.c + * arch/sh/drivers/pci/ops-sh7786.c + * Copyright (C) 2009 - 2011 Paul Mundt + * + * Author: Phil Edworthy <phil.edworthy@renesas.com> + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/msi.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of_pci.h> +#include <linux/of_platform.h> +#include <linux/pci.h> +#include <linux/phy/phy.h> + +#include "pcie-rcar.h" + +struct rcar_msi { + DECLARE_BITMAP(used, INT_PCI_MSI_NR); + struct irq_domain *domain; + struct msi_controller chip; + unsigned long pages; + struct mutex lock; /* serializes msi */ + int irq1; + int irq2; +}; + +static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip) +{ + return container_of(chip, struct rcar_msi, chip); +} + +/* Structure representing the PCIe interface */ +struct rcar_pcie { + struct device *dev; + struct phy *phy; + void __iomem *base; + struct list_head resources; + int root_bus_nr; + struct clk *bus_clk; + struct rcar_msi msi; +}; + +static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) +{ + unsigned int shift = BITS_PER_BYTE * (where & 3); + u32 val = rcar_pci_read_reg(pcie->base, where & ~3); + + return val >> shift; +} + +/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ +static int rcar_pcie_config_access(struct rcar_pcie *pcie, + unsigned char access_type, + struct pci_bus *bus, unsigned int devfn, + int where, u32 *data) +{ + unsigned int dev, func, reg, index; + + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + reg = where & ~3; + index = reg / 4; + + /* + * While each channel has its own memory-mapped extended config + * space, it's generally only accessible when in endpoint mode. + * When in root complex mode, the controller is unable to target + * itself with either type 0 or type 1 accesses, and indeed, any + * controller initiated target transfer to its own config space + * result in a completer abort. + * + * Each channel effectively only supports a single device, but as + * the same channel <-> device access works for any PCI_SLOT() + * value, we cheat a bit here and bind the controller's config + * space to devfn 0 in order to enable self-enumeration. In this + * case the regular ECAR/ECDR path is sidelined and the mangled + * config access itself is initiated as an internal bus transaction. + */ + if (pci_is_root_bus(bus)) { + if (dev != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (access_type == RCAR_PCI_ACCESS_READ) { + *data = rcar_pci_read_reg(pcie->base, PCICONF(index)); + } else { + /* Keep an eye out for changes to the root bus number */ + if (pci_is_root_bus(bus) && reg == PCI_PRIMARY_BUS) + pcie->root_bus_nr = *data & 0xff; + + rcar_pci_write_reg(pcie->base, *data, PCICONF(index)); + } + + return PCIBIOS_SUCCESSFUL; + } + + if (pcie->root_bus_nr < 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* Clear errors */ + rcar_pci_write_reg(pcie->base, rcar_pci_read_reg(pcie->base, PCIEERRFR), + PCIEERRFR); + + /* Set the PIO address */ + rcar_pci_write_reg(pcie->base, PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); + + /* Enable the configuration access */ + if (bus->parent->number == pcie->root_bus_nr) + rcar_pci_write_reg(pcie->base, + CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR); + else + rcar_pci_write_reg(pcie->base, + CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR); + + /* Check for errors */ + if (rcar_pci_read_reg(pcie->base, PCIEERRFR) & UNSUPPORTED_REQUEST) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* Check for master and target aborts */ + if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & + (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (access_type == RCAR_PCI_ACCESS_READ) + *data = rcar_pci_read_reg(pcie->base, PCIECDR); + else + rcar_pci_write_reg(pcie->base, *data, PCIECDR); + + /* Disable the configuration access */ + rcar_pci_write_reg(pcie->base, 0, PCIECCTLR); + + return PCIBIOS_SUCCESSFUL; +} + +static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + struct rcar_pcie *pcie = bus->sysdata; + int ret; + + ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ, + bus, devfn, where, val); + if (ret != PCIBIOS_SUCCESSFUL) { + *val = 0xffffffff; + return ret; + } + + if (size == 1) + *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff; + else if (size == 2) + *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff; + + dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", + bus->number, devfn, where, size, *val); + + return ret; +} + +/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ +static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + struct rcar_pcie *pcie = bus->sysdata; + unsigned int shift; + u32 data; + int ret; + + ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ, + bus, devfn, where, &data); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + + dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", + bus->number, devfn, where, size, val); + + if (size == 1) { + shift = BITS_PER_BYTE * (where & 3); + data &= ~(0xff << shift); + data |= ((val & 0xff) << shift); + } else if (size == 2) { + shift = BITS_PER_BYTE * (where & 2); + data &= ~(0xffff << shift); + data |= ((val & 0xffff) << shift); + } else { + data = val; + } + + ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE, + bus, devfn, where, &data); + + return ret; +} + +static struct pci_ops rcar_pcie_ops = { + .read = rcar_pcie_read_conf, + .write = rcar_pcie_write_conf, +}; + +static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci) +{ + struct resource_entry *win; + int i = 0; + + /* Setup PCI resources */ + resource_list_for_each_entry(win, &pci->resources) { + struct resource *res = win->res; + + if (!res->flags) + continue; + + switch (resource_type(res)) { + case IORESOURCE_IO: + case IORESOURCE_MEM: + rcar_pcie_set_outbound(i, pci->base, res, true); + i++; + break; + case IORESOURCE_BUS: + pci->root_bus_nr = res->start; + break; + default: + continue; + } + + pci_add_resource(resource, res); + } + + return 1; +} + +static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) +{ + struct device *dev = pcie->dev; + unsigned int timeout = 1000; + u32 macsr; + + if ((rcar_pci_read_reg(pcie->base, MACS2R) & LINK_SPEED) != + LINK_SPEED_5_0GTS) + return; + + if (rcar_pci_read_reg(pcie->base, MACCTLR) & SPEED_CHANGE) { + dev_err(dev, "Speed change already in progress\n"); + return; + } + + macsr = rcar_pci_read_reg(pcie->base, MACSR); + if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) + goto done; + + /* Set target link speed to 5.0 GT/s */ + rcar_rmw32(pcie->base, EXPCAP(12), PCI_EXP_LNKSTA_CLS, + PCI_EXP_LNKSTA_CLS_5_0GB); + + /* Set speed change reason as intentional factor */ + rcar_rmw32(pcie->base, MACCGSPSETR, SPCNGRSN, 0); + + /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ + if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) + rcar_pci_write_reg(pcie->base, macsr, MACSR); + + /* Start link speed change */ + rcar_rmw32(pcie->base, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); + + while (timeout--) { + macsr = rcar_pci_read_reg(pcie->base, MACSR); + if (macsr & SPCHGFIN) { + /* Clear the interrupt bits */ + rcar_pci_write_reg(pcie->base, macsr, MACSR); + + if (macsr & SPCHGFAIL) + dev_err(dev, "Speed change failed\n"); + + goto done; + } + + usleep_range(1000, 2000); + } + + dev_err(dev, "Speed change timed out\n"); + +done: + dev_info(dev, "Current link speed is %s GT/s\n", + (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); +} + +static int rcar_pcie_enable(struct rcar_pcie *pcie) +{ + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); + struct device *dev = pcie->dev; + struct pci_bus *bus, *child; + int ret; + + /* Try setting 5 GT/s link speed */ + rcar_pcie_force_speedup(pcie); + + rcar_pcie_setup(&bridge->windows, pcie); + + pci_add_flags(PCI_REASSIGN_ALL_BUS); + + bridge->dev.parent = dev; + bridge->sysdata = pcie; + bridge->busnr = pcie->root_bus_nr; + bridge->ops = &rcar_pcie_ops; + bridge->map_irq = of_irq_parse_and_map_pci; + bridge->swizzle_irq = pci_common_swizzle; + if (IS_ENABLED(CONFIG_PCI_MSI)) + bridge->msi = &pcie->msi.chip; + + ret = pci_scan_root_bus_bridge(bridge); + if (ret < 0) + return ret; + + bus = bridge->bus; + + pci_bus_size_bridges(bus); + pci_bus_assign_resources(bus); + + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + + pci_bus_add_devices(bus); + + return 0; +} + +static int phy_wait_for_ack(struct rcar_pcie *pcie) +{ + struct device *dev = pcie->dev; + unsigned int timeout = 100; + + while (timeout--) { + if (rcar_pci_read_reg(pcie->base, H1_PCIEPHYADRR) & PHY_ACK) + return 0; + + usleep_range(90, 110); + } + + dev_err(dev, "Access to PCIe phy timed out\n"); + + return -ETIMEDOUT; +} + +static void phy_write_reg(struct rcar_pcie *pcie, + unsigned int rate, u32 addr, + unsigned int lane, u32 data) +{ + u32 phyaddr; + + phyaddr = WRITE_CMD | + ((rate & 1) << RATE_POS) | + ((lane & 0xf) << LANE_POS) | + ((addr & 0xff) << ADR_POS); + + /* Set write data */ + rcar_pci_write_reg(pcie->base, data, H1_PCIEPHYDOUTR); + rcar_pci_write_reg(pcie->base, phyaddr, H1_PCIEPHYADRR); + + /* Ignore errors as they will be dealt with if the data link is down */ + phy_wait_for_ack(pcie); + + /* Clear command */ + rcar_pci_write_reg(pcie->base, 0, H1_PCIEPHYDOUTR); + rcar_pci_write_reg(pcie->base, 0, H1_PCIEPHYADRR); + + /* Ignore errors as they will be dealt with if the data link is down */ + phy_wait_for_ack(pcie); +} + +static int rcar_pcie_hw_init(struct rcar_pcie *pcie) +{ + int err; + + /* Begin initialization */ + rcar_pci_write_reg(pcie->base, 0, PCIETCTLR); + + /* Set mode */ + rcar_pci_write_reg(pcie->base, 1, PCIEMSR); + + err = rcar_pcie_wait_for_phyrdy(pcie->base); + if (err) + return err; + + /* + * Initial header for port config space is type 1, set the device + * class to match. Hardware takes care of propagating the IDSETR + * settings, so there is no need to bother with a quirk. + */ + rcar_pci_write_reg(pcie->base, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1); + + /* + * Setup Secondary Bus Number & Subordinate Bus Number, even though + * they aren't used, to avoid bridge being detected as broken. + */ + rcar_rmw32(pcie->base, RCONF(PCI_SECONDARY_BUS), 0xff, 1); + rcar_rmw32(pcie->base, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); + + /* Initialize default capabilities. */ + rcar_rmw32(pcie->base, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); + rcar_rmw32(pcie->base, REXPCAP(PCI_EXP_FLAGS), + PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); + rcar_rmw32(pcie->base, RCONF(PCI_HEADER_TYPE), 0x7f, + PCI_HEADER_TYPE_BRIDGE); + + /* Enable data link layer active state reporting */ + rcar_rmw32(pcie->base, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, + PCI_EXP_LNKCAP_DLLLARC); + + /* Write out the physical slot number = 0 */ + rcar_rmw32(pcie->base, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); + + /* Set the completion timer timeout to the maximum 50ms. */ + rcar_rmw32(pcie->base, TLCTLR + 1, 0x3f, 50); + + /* Terminate list of capabilities (Next Capability Offset=0) */ + rcar_rmw32(pcie->base, RVCCAP(0), 0xfff00000, 0); + + /* Enable MSI */ + if (IS_ENABLED(CONFIG_PCI_MSI)) + rcar_pci_write_reg(pcie->base, 0x801f0000, PCIEMSITXR); + + /* Finish initialization - establish a PCI Express link */ + rcar_pci_write_reg(pcie->base, CFINIT, PCIETCTLR); + + /* This will timeout if we don't have a link. */ + err = rcar_pcie_wait_for_dl(pcie->base); + if (err) + return err; + + /* Enable INTx interrupts */ + rcar_rmw32(pcie->base, PCIEINTXR, 0, 0xF << 8); + + /* flush modifications */ + wmb(); + + return 0; +} + +static int rcar_pcie_phy_init_h1(struct rcar_pcie *pcie) +{ + /* Initialize the phy */ + phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); + phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); + phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); + phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); + phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); + phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); + phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); + phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); + phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); + phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); + phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); + phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); + + phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); + phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); + phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); + + return 0; +} + +static int rcar_pcie_phy_init_gen2(struct rcar_pcie *pcie) +{ + /* + * These settings come from the R-Car Series, 2nd Generation User's + * Manual, section 50.3.1 (2) Initialization of the physical layer. + */ + rcar_pci_write_reg(pcie->base, 0x000f0030, GEN2_PCIEPHYADDR); + rcar_pci_write_reg(pcie->base, 0x00381203, GEN2_PCIEPHYDATA); + rcar_pci_write_reg(pcie->base, 0x00000001, GEN2_PCIEPHYCTRL); + rcar_pci_write_reg(pcie->base, 0x00000006, GEN2_PCIEPHYCTRL); + + rcar_pci_write_reg(pcie->base, 0x000f0054, GEN2_PCIEPHYADDR); + /* The following value is for DC connection, no termination resistor */ + rcar_pci_write_reg(pcie->base, 0x13802007, GEN2_PCIEPHYDATA); + rcar_pci_write_reg(pcie->base, 0x00000001, GEN2_PCIEPHYCTRL); + rcar_pci_write_reg(pcie->base, 0x00000006, GEN2_PCIEPHYCTRL); + + return 0; +} + +static int rcar_pcie_phy_init_gen3(struct rcar_pcie *pcie) +{ + int err; + + err = phy_init(pcie->phy); + if (err) + return err; + + err = phy_power_on(pcie->phy); + if (err) + phy_exit(pcie->phy); + + return err; +} + +static int rcar_msi_alloc(struct rcar_msi *chip) +{ + int msi; + + mutex_lock(&chip->lock); + + msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR); + if (msi < INT_PCI_MSI_NR) + set_bit(msi, chip->used); + else + msi = -ENOSPC; + + mutex_unlock(&chip->lock); + + return msi; +} + +static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs) +{ + int msi; + + mutex_lock(&chip->lock); + msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR, + order_base_2(no_irqs)); + mutex_unlock(&chip->lock); + + return msi; +} + +static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq) +{ + mutex_lock(&chip->lock); + clear_bit(irq, chip->used); + mutex_unlock(&chip->lock); +} + +static irqreturn_t rcar_pcie_msi_irq(int irq, void *data) +{ + struct rcar_pcie *pcie = data; + struct rcar_msi *msi = &pcie->msi; + struct device *dev = pcie->dev; + unsigned long reg; + + reg = rcar_pci_read_reg(pcie->base, PCIEMSIFR); + + /* MSI & INTx share an interrupt - we only handle MSI here */ + if (!reg) + return IRQ_NONE; + + while (reg) { + unsigned int index = find_first_bit(®, 32); + unsigned int msi_irq; + + /* clear the interrupt */ + rcar_pci_write_reg(pcie->base, 1 << index, PCIEMSIFR); + + msi_irq = irq_find_mapping(msi->domain, index); + if (msi_irq) { + if (test_bit(index, msi->used)) + generic_handle_irq(msi_irq); + else + dev_info(dev, "unhandled MSI\n"); + } else { + /* Unknown MSI, just clear it */ + dev_dbg(dev, "unexpected MSI\n"); + } + + /* see if there's any more pending in this vector */ + reg = rcar_pci_read_reg(pcie->base, PCIEMSIFR); + } + + return IRQ_HANDLED; +} + +static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, + struct msi_desc *desc) +{ + struct rcar_msi *msi = to_rcar_msi(chip); + struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip); + struct msi_msg msg; + unsigned int irq; + int hwirq; + + hwirq = rcar_msi_alloc(msi); + if (hwirq < 0) + return hwirq; + + irq = irq_find_mapping(msi->domain, hwirq); + if (!irq) { + rcar_msi_free(msi, hwirq); + return -EINVAL; + } + + irq_set_msi_desc(irq, desc); + + msg.address_lo = rcar_pci_read_reg(pcie->base, PCIEMSIALR) & ~MSIFE; + msg.address_hi = rcar_pci_read_reg(pcie->base, PCIEMSIAUR); + msg.data = hwirq; + + pci_write_msi_msg(irq, &msg); + + return 0; +} + +static int rcar_msi_setup_irqs(struct msi_controller *chip, + struct pci_dev *pdev, int nvec, int type) +{ + struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip); + struct rcar_msi *msi = to_rcar_msi(chip); + struct msi_desc *desc; + struct msi_msg msg; + unsigned int irq; + int hwirq; + int i; + + /* MSI-X interrupts are not supported */ + if (type == PCI_CAP_ID_MSIX) + return -EINVAL; + + WARN_ON(!list_is_singular(&pdev->dev.msi_list)); + desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list); + + hwirq = rcar_msi_alloc_region(msi, nvec); + if (hwirq < 0) + return -ENOSPC; + + irq = irq_find_mapping(msi->domain, hwirq); + if (!irq) + return -ENOSPC; + + for (i = 0; i < nvec; i++) { + /* + * irq_create_mapping() called from rcar_pcie_probe() pre- + * allocates descs, so there is no need to allocate descs here. + * We can therefore assume that if irq_find_mapping() above + * returns non-zero, then the descs are also successfully + * allocated. + */ + if (irq_set_msi_desc_off(irq, i, desc)) { + /* TODO: clear */ + return -EINVAL; + } + } + + desc->nvec_used = nvec; + desc->msi_attrib.multiple = order_base_2(nvec); + + msg.address_lo = rcar_pci_read_reg(pcie->base, PCIEMSIALR) & ~MSIFE; + msg.address_hi = rcar_pci_read_reg(pcie->base, PCIEMSIAUR); + msg.data = hwirq; + + pci_write_msi_msg(irq, &msg); + + return 0; +} + +static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) +{ + struct irq_data *d = irq_get_irq_data(irq); + struct rcar_msi *msi = to_rcar_msi(chip); + + rcar_msi_free(msi, d->hwirq); +} + +static struct irq_chip rcar_msi_irq_chip = { + .name = "R-Car PCIe MSI", + .irq_enable = pci_msi_unmask_irq, + .irq_disable = pci_msi_mask_irq, + .irq_mask = pci_msi_mask_irq, + .irq_unmask = pci_msi_unmask_irq, +}; + +static int rcar_msi_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops msi_domain_ops = { + .map = rcar_msi_map, +}; + +static void rcar_pcie_unmap_msi(struct rcar_pcie *pcie) +{ + struct rcar_msi *msi = &pcie->msi; + int i, irq; + + for (i = 0; i < INT_PCI_MSI_NR; i++) { + irq = irq_find_mapping(msi->domain, i); + if (irq > 0) + irq_dispose_mapping(irq); + } + + irq_domain_remove(msi->domain); +} + +static int rcar_pcie_enable_msi(struct rcar_pcie *pcie) +{ + struct rcar_msi *msi = &pcie->msi; + struct device *dev = pcie->dev; + phys_addr_t base; + int err, i; + + mutex_init(&msi->lock); + + msi->chip.dev = dev; + msi->chip.setup_irq = rcar_msi_setup_irq; + msi->chip.setup_irqs = rcar_msi_setup_irqs; + msi->chip.teardown_irq = rcar_msi_teardown_irq; + + msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR, + &msi_domain_ops, &msi->chip); + if (!msi->domain) { + dev_err(dev, "failed to create IRQ domain\n"); + return -ENOMEM; + } + + for (i = 0; i < INT_PCI_MSI_NR; i++) + irq_create_mapping(msi->domain, i); + + /* Two irqs are for MSI, but they are also used for non-MSI irqs */ + err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq, + IRQF_SHARED | IRQF_NO_THREAD, + rcar_msi_irq_chip.name, pcie); + if (err < 0) { + dev_err(dev, "failed to request IRQ: %d\n", err); + goto err; + } + + err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq, + IRQF_SHARED | IRQF_NO_THREAD, + rcar_msi_irq_chip.name, pcie); + if (err < 0) { + dev_err(dev, "failed to request IRQ: %d\n", err); + goto err; + } + + /* setup MSI data target */ + msi->pages = __get_free_pages(GFP_KERNEL, 0); + if (!msi->pages) { + err = -ENOMEM; + goto err; + } + base = virt_to_phys((void *)msi->pages); + + rcar_pci_write_reg(pcie->base, lower_32_bits(base) | MSIFE, PCIEMSIALR); + rcar_pci_write_reg(pcie->base, upper_32_bits(base), PCIEMSIAUR); + + /* enable all MSI interrupts */ + rcar_pci_write_reg(pcie->base, 0xffffffff, PCIEMSIIER); + + return 0; + +err: + rcar_pcie_unmap_msi(pcie); + return err; +} + +static void rcar_pcie_teardown_msi(struct rcar_pcie *pcie) +{ + struct rcar_msi *msi = &pcie->msi; + + /* Disable all MSI interrupts */ + rcar_pci_write_reg(pcie->base, 0, PCIEMSIIER); + + /* Disable address decoding of the MSI interrupt, MSIFE */ + rcar_pci_write_reg(pcie->base, 0, PCIEMSIALR); + + free_pages(msi->pages, 0); + + rcar_pcie_unmap_msi(pcie); +} + +static int rcar_pcie_get_resources(struct rcar_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct resource res; + int err, i; + + pcie->phy = devm_phy_optional_get(dev, "pcie"); + if (IS_ERR(pcie->phy)) + return PTR_ERR(pcie->phy); + + err = of_address_to_resource(dev->of_node, 0, &res); + if (err) + return err; + + pcie->base = devm_ioremap_resource(dev, &res); + if (IS_ERR(pcie->base)) + return PTR_ERR(pcie->base); + + pcie->bus_clk = devm_clk_get(dev, "pcie_bus"); + if (IS_ERR(pcie->bus_clk)) { + dev_err(dev, "cannot get pcie bus clock\n"); + return PTR_ERR(pcie->bus_clk); + } + + i = irq_of_parse_and_map(dev->of_node, 0); + if (!i) { + dev_err(dev, "cannot get platform resources for msi interrupt\n"); + err = -ENOENT; + goto err_irq1; + } + pcie->msi.irq1 = i; + + i = irq_of_parse_and_map(dev->of_node, 1); + if (!i) { + dev_err(dev, "cannot get platform resources for msi interrupt\n"); + err = -ENOENT; + goto err_irq2; + } + pcie->msi.irq2 = i; + + return 0; + +err_irq2: + irq_dispose_mapping(pcie->msi.irq1); +err_irq1: + return err; +} + +static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, + struct of_pci_range *range, + int *index) +{ + u64 restype = range->flags; + u64 cpu_addr = range->cpu_addr; + u64 cpu_end = range->cpu_addr + range->size; + u64 pci_addr = range->pci_addr; + u32 flags = LAM_64BIT | LAR_ENABLE; + u64 mask; + u64 size; + int idx = *index; + + if (restype & IORESOURCE_PREFETCH) + flags |= LAM_PREFETCH; + + /* + * If the size of the range is larger than the alignment of the start + * address, we have to use multiple entries to perform the mapping. + */ + if (cpu_addr > 0) { + unsigned long nr_zeros = __ffs64(cpu_addr); + u64 alignment = 1ULL << nr_zeros; + + size = min(range->size, alignment); + } else { + size = range->size; + } + /* Hardware supports max 4GiB inbound region */ + size = min(size, 1ULL << 32); + + mask = roundup_pow_of_two(size) - 1; + mask &= ~0xf; + + while (cpu_addr < cpu_end) { + rcar_pcie_set_inbound(pcie->base, cpu_addr, pci_addr, + mask | flags, idx, true); + + pci_addr += size; + cpu_addr += size; + idx += 2; + + if (idx > MAX_NR_INBOUND_MAPS) { + dev_err(pcie->dev, "Failed to map inbound regions!\n"); + return -EINVAL; + } + } + *index = idx; + + return 0; +} + +static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie, + struct device_node *np) +{ + struct of_pci_range_parser parser; + struct of_pci_range range; + int index = 0; + int err; + + if (of_pci_dma_range_parser_init(&parser, np)) + return -EINVAL; + + /* Get the dma-ranges from DT */ + for_each_of_pci_range(&parser, &range) { + u64 end = range.cpu_addr + range.size - 1; + + dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", + range.flags, range.cpu_addr, end, range.pci_addr); + + err = rcar_pcie_inbound_ranges(pcie, &range, &index); + if (err) + return err; + } + + return 0; +} + +static const struct of_device_id rcar_pcie_of_match[] = { + { .compatible = "renesas,pcie-r8a7779", + .data = rcar_pcie_phy_init_h1 }, + { .compatible = "renesas,pcie-r8a7790", + .data = rcar_pcie_phy_init_gen2 }, + { .compatible = "renesas,pcie-r8a7791", + .data = rcar_pcie_phy_init_gen2 }, + { .compatible = "renesas,pcie-rcar-gen2", + .data = rcar_pcie_phy_init_gen2 }, + { .compatible = "renesas,pcie-r8a7795", + .data = rcar_pcie_phy_init_gen3 }, + { .compatible = "renesas,pcie-rcar-gen3", + .data = rcar_pcie_phy_init_gen3 }, + {}, +}; + +static int rcar_pcie_probe(struct platform_device *pdev) +{ + int (*phy_init_fn)(struct rcar_pcie *pcie); + struct device *dev = &pdev->dev; + struct pci_host_bridge *bridge; + struct rcar_pcie *pcie; + u32 data; + int err; + + bridge = pci_alloc_host_bridge(sizeof(*pcie)); + if (!bridge) + return -ENOMEM; + + pcie = pci_host_bridge_priv(bridge); + + pcie->dev = dev; + platform_set_drvdata(pdev, pcie); + + err = pci_parse_request_of_pci_ranges(dev, &pcie->resources, NULL); + if (err) + goto err_free_bridge; + + pm_runtime_enable(pcie->dev); + err = pm_runtime_get_sync(pcie->dev); + if (err < 0) { + dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); + goto err_pm_disable; + } + + err = rcar_pcie_get_resources(pcie); + if (err < 0) { + dev_err(dev, "failed to request resources: %d\n", err); + goto err_pm_put; + } + + err = clk_prepare_enable(pcie->bus_clk); + if (err) { + dev_err(dev, "failed to enable bus clock: %d\n", err); + goto err_unmap_msi_irqs; + } + + err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node); + if (err) + goto err_clk_disable; + + phy_init_fn = of_device_get_match_data(dev); + err = phy_init_fn(pcie); + if (err) { + dev_err(dev, "failed to init PCIe PHY\n"); + goto err_clk_disable; + } + + /* Failure to get a link might just be that no cards are inserted */ + if (rcar_pcie_hw_init(pcie)) { + dev_info(dev, "PCIe link down\n"); + err = -ENODEV; + goto err_phy_shutdown; + } + + data = rcar_pci_read_reg(pcie->base, MACSR); + dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + err = rcar_pcie_enable_msi(pcie); + if (err < 0) { + dev_err(dev, + "failed to enable MSI support: %d\n", + err); + goto err_phy_shutdown; + } + } + + err = rcar_pcie_enable(pcie); + if (err) + goto err_msi_teardown; + + return 0; + +err_msi_teardown: + if (IS_ENABLED(CONFIG_PCI_MSI)) + rcar_pcie_teardown_msi(pcie); + +err_phy_shutdown: + if (pcie->phy) { + phy_power_off(pcie->phy); + phy_exit(pcie->phy); + } + +err_clk_disable: + clk_disable_unprepare(pcie->bus_clk); + +err_unmap_msi_irqs: + irq_dispose_mapping(pcie->msi.irq2); + irq_dispose_mapping(pcie->msi.irq1); + +err_pm_put: + pm_runtime_put(dev); + +err_pm_disable: + pm_runtime_disable(dev); + pci_free_resource_list(&pcie->resources); + +err_free_bridge: + pci_free_host_bridge(bridge); + + return err; +} + +static int rcar_pcie_resume_noirq(struct device *dev) +{ + struct rcar_pcie *pcie = dev_get_drvdata(dev); + + if (rcar_pci_read_reg(pcie->base, PMSR) && + !(rcar_pci_read_reg(pcie->base, PCIETCTLR) & DL_DOWN)) + return 0; + + /* Re-establish the PCIe link */ + rcar_pci_write_reg(pcie->base, CFINIT, PCIETCTLR); + return rcar_pcie_wait_for_dl(pcie->base); +} + +static const struct dev_pm_ops rcar_pcie_pm_ops = { + .resume_noirq = rcar_pcie_resume_noirq, +}; + +static struct platform_driver rcar_pcie_driver = { + .driver = { + .name = "rcar-pcie", + .of_match_table = rcar_pcie_of_match, + .pm = &rcar_pcie_pm_ops, + .suppress_bind_attrs = true, + }, + .probe = rcar_pcie_probe, +}; +builtin_platform_driver(rcar_pcie_driver); diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c index f6a669a..1008ae6 100644 --- a/drivers/pci/controller/pcie-rcar.c +++ b/drivers/pci/controller/pcie-rcar.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * PCIe driver for Renesas R-Car SoCs - * Copyright (C) 2014 Renesas Electronics Europe Ltd + * Copyright (C) 2014-2019 Renesas Electronics Europe Ltd * * Based on: * arch/sh/drivers/pci/pcie-sh7786.c @@ -11,535 +11,80 @@ * Author: Phil Edworthy <phil.edworthy@renesas.com> */ -#include <linux/bitops.h> -#include <linux/clk.h> #include <linux/delay.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/msi.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <linux/of_pci.h> -#include <linux/of_platform.h> #include <linux/pci.h> -#include <linux/phy/phy.h> -#include <linux/platform_device.h> -#include <linux/pm_runtime.h> -#include <linux/slab.h> -#include "../pci.h" +#include "pcie-rcar.h" -#define PCIECAR 0x000010 -#define PCIECCTLR 0x000018 -#define CONFIG_SEND_ENABLE BIT(31) -#define TYPE0 (0 << 8) -#define TYPE1 BIT(8) -#define PCIECDR 0x000020 -#define PCIEMSR 0x000028 -#define PCIEINTXR 0x000400 -#define PCIEPHYSR 0x0007f0 -#define PHYRDY BIT(0) -#define PCIEMSITXR 0x000840 - -/* Transfer control */ -#define PCIETCTLR 0x02000 -#define DL_DOWN BIT(3) -#define CFINIT BIT(0) -#define PCIETSTR 0x02004 -#define DATA_LINK_ACTIVE BIT(0) -#define PCIEERRFR 0x02020 -#define UNSUPPORTED_REQUEST BIT(4) -#define PCIEMSIFR 0x02044 -#define PCIEMSIALR 0x02048 -#define MSIFE BIT(0) -#define PCIEMSIAUR 0x0204c -#define PCIEMSIIER 0x02050 - -/* root port address */ -#define PCIEPRAR(x) (0x02080 + ((x) * 0x4)) - -/* local address reg & mask */ -#define PCIELAR(x) (0x02200 + ((x) * 0x20)) -#define PCIELAMR(x) (0x02208 + ((x) * 0x20)) -#define LAM_PREFETCH BIT(3) -#define LAM_64BIT BIT(2) -#define LAR_ENABLE BIT(1) - -/* PCIe address reg & mask */ -#define PCIEPALR(x) (0x03400 + ((x) * 0x20)) -#define PCIEPAUR(x) (0x03404 + ((x) * 0x20)) -#define PCIEPAMR(x) (0x03408 + ((x) * 0x20)) -#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20)) -#define PAR_ENABLE BIT(31) -#define IO_SPACE BIT(8) - -/* Configuration */ -#define PCICONF(x) (0x010000 + ((x) * 0x4)) -#define PMCAP(x) (0x010040 + ((x) * 0x4)) -#define EXPCAP(x) (0x010070 + ((x) * 0x4)) -#define VCCAP(x) (0x010100 + ((x) * 0x4)) - -/* link layer */ -#define IDSETR1 0x011004 -#define TLCTLR 0x011048 -#define MACSR 0x011054 -#define SPCHGFIN BIT(4) -#define SPCHGFAIL BIT(6) -#define SPCHGSUC BIT(7) -#define LINK_SPEED (0xf << 16) -#define LINK_SPEED_2_5GTS (1 << 16) -#define LINK_SPEED_5_0GTS (2 << 16) -#define MACCTLR 0x011058 -#define SPEED_CHANGE BIT(24) -#define SCRAMBLE_DISABLE BIT(27) -#define PMSR 0x01105c -#define MACS2R 0x011078 -#define MACCGSPSETR 0x011084 -#define SPCNGRSN BIT(31) - -/* R-Car H1 PHY */ -#define H1_PCIEPHYADRR 0x04000c -#define WRITE_CMD BIT(16) -#define PHY_ACK BIT(24) -#define RATE_POS 12 -#define LANE_POS 8 -#define ADR_POS 0 -#define H1_PCIEPHYDOUTR 0x040014 - -/* R-Car Gen2 PHY */ -#define GEN2_PCIEPHYADDR 0x780 -#define GEN2_PCIEPHYDATA 0x784 -#define GEN2_PCIEPHYCTRL 0x78c - -#define INT_PCI_MSI_NR 32 - -#define RCONF(x) (PCICONF(0) + (x)) -#define RPMCAP(x) (PMCAP(0) + (x)) -#define REXPCAP(x) (EXPCAP(0) + (x)) -#define RVCCAP(x) (VCCAP(0) + (x)) - -#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24) -#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19) -#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16) - -#define RCAR_PCI_MAX_RESOURCES 4 -#define MAX_NR_INBOUND_MAPS 6 - -struct rcar_msi { - DECLARE_BITMAP(used, INT_PCI_MSI_NR); - struct irq_domain *domain; - struct msi_controller chip; - unsigned long pages; - struct mutex lock; - int irq1; - int irq2; -}; - -static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip) -{ - return container_of(chip, struct rcar_msi, chip); -} - -/* Structure representing the PCIe interface */ -struct rcar_pcie { - struct device *dev; - struct phy *phy; - void __iomem *base; - struct list_head resources; - int root_bus_nr; - struct clk *bus_clk; - struct rcar_msi msi; -}; - -static void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, - unsigned int reg) +void rcar_pci_write_reg(void __iomem *base, u32 val, unsigned int reg) { - writel(val, pcie->base + reg); + writel(val, base + reg); } -static u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) +u32 rcar_pci_read_reg(void __iomem *base, unsigned int reg) { - return readl(pcie->base + reg); + return readl(base + reg); } -enum { - RCAR_PCI_ACCESS_READ, - RCAR_PCI_ACCESS_WRITE, -}; - -static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) +void rcar_rmw32(void __iomem *base, int where, u32 mask, u32 data) { unsigned int shift = BITS_PER_BYTE * (where & 3); - u32 val = rcar_pci_read_reg(pcie, where & ~3); + u32 val = rcar_pci_read_reg(base, where & ~3); val &= ~(mask << shift); val |= data << shift; - rcar_pci_write_reg(pcie, val, where & ~3); -} - -static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) -{ - unsigned int shift = BITS_PER_BYTE * (where & 3); - u32 val = rcar_pci_read_reg(pcie, where & ~3); - - return val >> shift; + rcar_pci_write_reg(base, val, where & ~3); } -/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ -static int rcar_pcie_config_access(struct rcar_pcie *pcie, - unsigned char access_type, struct pci_bus *bus, - unsigned int devfn, int where, u32 *data) -{ - unsigned int dev, func, reg, index; - - dev = PCI_SLOT(devfn); - func = PCI_FUNC(devfn); - reg = where & ~3; - index = reg / 4; - - /* - * While each channel has its own memory-mapped extended config - * space, it's generally only accessible when in endpoint mode. - * When in root complex mode, the controller is unable to target - * itself with either type 0 or type 1 accesses, and indeed, any - * controller initiated target transfer to its own config space - * result in a completer abort. - * - * Each channel effectively only supports a single device, but as - * the same channel <-> device access works for any PCI_SLOT() - * value, we cheat a bit here and bind the controller's config - * space to devfn 0 in order to enable self-enumeration. In this - * case the regular ECAR/ECDR path is sidelined and the mangled - * config access itself is initiated as an internal bus transaction. - */ - if (pci_is_root_bus(bus)) { - if (dev != 0) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (access_type == RCAR_PCI_ACCESS_READ) { - *data = rcar_pci_read_reg(pcie, PCICONF(index)); - } else { - /* Keep an eye out for changes to the root bus number */ - if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS)) - pcie->root_bus_nr = *data & 0xff; - - rcar_pci_write_reg(pcie, *data, PCICONF(index)); - } - - return PCIBIOS_SUCCESSFUL; - } - - if (pcie->root_bus_nr < 0) - return PCIBIOS_DEVICE_NOT_FOUND; - - /* Clear errors */ - rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); - - /* Set the PIO address */ - rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | - PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); - - /* Enable the configuration access */ - if (bus->parent->number == pcie->root_bus_nr) - rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR); - else - rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR); - - /* Check for errors */ - if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) - return PCIBIOS_DEVICE_NOT_FOUND; - - /* Check for master and target aborts */ - if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & - (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (access_type == RCAR_PCI_ACCESS_READ) - *data = rcar_pci_read_reg(pcie, PCIECDR); - else - rcar_pci_write_reg(pcie, *data, PCIECDR); - - /* Disable the configuration access */ - rcar_pci_write_reg(pcie, 0, PCIECCTLR); - - return PCIBIOS_SUCCESSFUL; -} - -static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - struct rcar_pcie *pcie = bus->sysdata; - int ret; - - ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ, - bus, devfn, where, val); - if (ret != PCIBIOS_SUCCESSFUL) { - *val = 0xffffffff; - return ret; - } - - if (size == 1) - *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff; - else if (size == 2) - *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff; - - dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", - bus->number, devfn, where, size, *val); - - return ret; -} - -/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ -static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - struct rcar_pcie *pcie = bus->sysdata; - unsigned int shift; - u32 data; - int ret; - - ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ, - bus, devfn, where, &data); - if (ret != PCIBIOS_SUCCESSFUL) - return ret; - - dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", - bus->number, devfn, where, size, val); - - if (size == 1) { - shift = BITS_PER_BYTE * (where & 3); - data &= ~(0xff << shift); - data |= ((val & 0xff) << shift); - } else if (size == 2) { - shift = BITS_PER_BYTE * (where & 2); - data &= ~(0xffff << shift); - data |= ((val & 0xffff) << shift); - } else - data = val; - - ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE, - bus, devfn, where, &data); - - return ret; -} - -static struct pci_ops rcar_pcie_ops = { - .read = rcar_pcie_read_conf, - .write = rcar_pcie_write_conf, -}; - -static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie, - struct resource *res) +void rcar_pcie_set_outbound(int win, void __iomem *base, + struct resource *res, bool host) { /* Setup PCIe address space mappings for each resource */ - resource_size_t size; - resource_size_t res_start; - u32 mask; - - rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win)); + resource_size_t size = 0; + resource_size_t res_start = 0; + u32 mask = 0x0; + rcar_pci_write_reg(base, mask, PCIEPTCTLR(win)); /* * The PAMR mask is calculated in units of 128Bytes, which * keeps things pretty simple. */ size = resource_size(res); - mask = (roundup_pow_of_two(size) / SZ_128) - 1; - rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win)); + if (size > 128) + mask = (roundup_pow_of_two(size) / SZ_128) - 1; + rcar_pci_write_reg(base, mask << 7, PCIEPAMR(win)); - if (res->flags & IORESOURCE_IO) - res_start = pci_pio_to_address(res->start); - else + if (!host) { res_start = res->start; + } else { + if (res->flags & IORESOURCE_IO) + res_start = pci_pio_to_address(res->start); + else + res_start = res->start; + } - rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win)); - rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F, + rcar_pci_write_reg(base, upper_32_bits(res_start), PCIEPAUR(win)); + rcar_pci_write_reg(base, lower_32_bits(res_start) & ~0x7F, PCIEPALR(win)); - /* First resource is for IO */ - mask = PAR_ENABLE; + mask = 0x0; + if (res->start) + mask = PAR_ENABLE; + if (res->flags & IORESOURCE_IO) mask |= IO_SPACE; - rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win)); -} - -static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci) -{ - struct resource_entry *win; - int i = 0; - - /* Setup PCI resources */ - resource_list_for_each_entry(win, &pci->resources) { - struct resource *res = win->res; - - if (!res->flags) - continue; - - switch (resource_type(res)) { - case IORESOURCE_IO: - case IORESOURCE_MEM: - rcar_pcie_setup_window(i, pci, res); - i++; - break; - case IORESOURCE_BUS: - pci->root_bus_nr = res->start; - break; - default: - continue; - } - - pci_add_resource(resource, res); - } - - return 1; -} - -static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) -{ - struct device *dev = pcie->dev; - unsigned int timeout = 1000; - u32 macsr; - - if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) - return; - - if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { - dev_err(dev, "Speed change already in progress\n"); - return; - } - - macsr = rcar_pci_read_reg(pcie, MACSR); - if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) - goto done; - - /* Set target link speed to 5.0 GT/s */ - rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, - PCI_EXP_LNKSTA_CLS_5_0GB); - - /* Set speed change reason as intentional factor */ - rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); - - /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ - if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) - rcar_pci_write_reg(pcie, macsr, MACSR); - - /* Start link speed change */ - rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); - - while (timeout--) { - macsr = rcar_pci_read_reg(pcie, MACSR); - if (macsr & SPCHGFIN) { - /* Clear the interrupt bits */ - rcar_pci_write_reg(pcie, macsr, MACSR); - - if (macsr & SPCHGFAIL) - dev_err(dev, "Speed change failed\n"); - - goto done; - } - - msleep(1); - } - - dev_err(dev, "Speed change timed out\n"); - -done: - dev_info(dev, "Current link speed is %s GT/s\n", - (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); -} - -static int rcar_pcie_enable(struct rcar_pcie *pcie) -{ - struct device *dev = pcie->dev; - struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); - struct pci_bus *bus, *child; - int ret; - - /* Try setting 5 GT/s link speed */ - rcar_pcie_force_speedup(pcie); - - rcar_pcie_setup(&bridge->windows, pcie); - - pci_add_flags(PCI_REASSIGN_ALL_BUS); - - bridge->dev.parent = dev; - bridge->sysdata = pcie; - bridge->busnr = pcie->root_bus_nr; - bridge->ops = &rcar_pcie_ops; - bridge->map_irq = of_irq_parse_and_map_pci; - bridge->swizzle_irq = pci_common_swizzle; - if (IS_ENABLED(CONFIG_PCI_MSI)) - bridge->msi = &pcie->msi.chip; - - ret = pci_scan_root_bus_bridge(bridge); - if (ret < 0) - return ret; - - bus = bridge->bus; - - pci_bus_size_bridges(bus); - pci_bus_assign_resources(bus); - - list_for_each_entry(child, &bus->children, node) - pcie_bus_configure_settings(child); - - pci_bus_add_devices(bus); - - return 0; -} - -static int phy_wait_for_ack(struct rcar_pcie *pcie) -{ - struct device *dev = pcie->dev; - unsigned int timeout = 100; - - while (timeout--) { - if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) - return 0; - - udelay(100); - } - - dev_err(dev, "Access to PCIe phy timed out\n"); - - return -ETIMEDOUT; -} - -static void phy_write_reg(struct rcar_pcie *pcie, - unsigned int rate, u32 addr, - unsigned int lane, u32 data) -{ - u32 phyaddr; - - phyaddr = WRITE_CMD | - ((rate & 1) << RATE_POS) | - ((lane & 0xf) << LANE_POS) | - ((addr & 0xff) << ADR_POS); - - /* Set write data */ - rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); - rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); - - /* Ignore errors as they will be dealt with if the data link is down */ - phy_wait_for_ack(pcie); - - /* Clear command */ - rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); - rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); - - /* Ignore errors as they will be dealt with if the data link is down */ - phy_wait_for_ack(pcie); + rcar_pci_write_reg(base, mask, PCIEPTCTLR(win)); + /* flush modifications */ + wmb(); } -static int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie) +int rcar_pcie_wait_for_phyrdy(void __iomem *base) { unsigned int timeout = 10; while (timeout--) { - if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY) + if (rcar_pci_read_reg(base, PCIEPHYSR) & PHYRDY) return 0; msleep(5); @@ -548,12 +93,12 @@ static int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie) return -ETIMEDOUT; } -static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie) +int rcar_pcie_wait_for_dl(void __iomem *base) { unsigned int timeout = 10000; while (timeout--) { - if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE)) + if ((rcar_pci_read_reg(base, PCIETSTR) & DATA_LINK_ACTIVE)) return 0; udelay(5); @@ -563,695 +108,27 @@ static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie) return -ETIMEDOUT; } -static int rcar_pcie_hw_init(struct rcar_pcie *pcie) -{ - int err; - - /* Begin initialization */ - rcar_pci_write_reg(pcie, 0, PCIETCTLR); - - /* Set mode */ - rcar_pci_write_reg(pcie, 1, PCIEMSR); - - err = rcar_pcie_wait_for_phyrdy(pcie); - if (err) - return err; - - /* - * Initial header for port config space is type 1, set the device - * class to match. Hardware takes care of propagating the IDSETR - * settings, so there is no need to bother with a quirk. - */ - rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1); - - /* - * Setup Secondary Bus Number & Subordinate Bus Number, even though - * they aren't used, to avoid bridge being detected as broken. - */ - rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); - rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); - - /* Initialize default capabilities. */ - rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); - rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), - PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); - rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, - PCI_HEADER_TYPE_BRIDGE); - - /* Enable data link layer active state reporting */ - rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, - PCI_EXP_LNKCAP_DLLLARC); - - /* Write out the physical slot number = 0 */ - rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); - - /* Set the completion timer timeout to the maximum 50ms. */ - rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); - - /* Terminate list of capabilities (Next Capability Offset=0) */ - rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); - - /* Enable MSI */ - if (IS_ENABLED(CONFIG_PCI_MSI)) - rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); - - /* Finish initialization - establish a PCI Express link */ - rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); - - /* This will timeout if we don't have a link. */ - err = rcar_pcie_wait_for_dl(pcie); - if (err) - return err; - - /* Enable INTx interrupts */ - rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); - - wmb(); - - return 0; -} - -static int rcar_pcie_phy_init_h1(struct rcar_pcie *pcie) -{ - /* Initialize the phy */ - phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); - phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); - phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); - phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); - phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); - phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); - phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); - phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); - phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); - phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); - phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); - phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); - - phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); - phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); - phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); - - return 0; -} - -static int rcar_pcie_phy_init_gen2(struct rcar_pcie *pcie) -{ - /* - * These settings come from the R-Car Series, 2nd Generation User's - * Manual, section 50.3.1 (2) Initialization of the physical layer. - */ - rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); - rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); - rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); - rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); - - rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); - /* The following value is for DC connection, no termination resistor */ - rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); - rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); - rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); - - return 0; -} - -static int rcar_pcie_phy_init_gen3(struct rcar_pcie *pcie) -{ - int err; - - err = phy_init(pcie->phy); - if (err) - return err; - - err = phy_power_on(pcie->phy); - if (err) - phy_exit(pcie->phy); - - return err; -} - -static int rcar_msi_alloc(struct rcar_msi *chip) -{ - int msi; - - mutex_lock(&chip->lock); - - msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR); - if (msi < INT_PCI_MSI_NR) - set_bit(msi, chip->used); - else - msi = -ENOSPC; - - mutex_unlock(&chip->lock); - - return msi; -} - -static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs) -{ - int msi; - - mutex_lock(&chip->lock); - msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR, - order_base_2(no_irqs)); - mutex_unlock(&chip->lock); - - return msi; -} - -static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq) -{ - mutex_lock(&chip->lock); - clear_bit(irq, chip->used); - mutex_unlock(&chip->lock); -} - -static irqreturn_t rcar_pcie_msi_irq(int irq, void *data) -{ - struct rcar_pcie *pcie = data; - struct rcar_msi *msi = &pcie->msi; - struct device *dev = pcie->dev; - unsigned long reg; - - reg = rcar_pci_read_reg(pcie, PCIEMSIFR); - - /* MSI & INTx share an interrupt - we only handle MSI here */ - if (!reg) - return IRQ_NONE; - - while (reg) { - unsigned int index = find_first_bit(®, 32); - unsigned int msi_irq; - - /* clear the interrupt */ - rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR); - - msi_irq = irq_find_mapping(msi->domain, index); - if (msi_irq) { - if (test_bit(index, msi->used)) - generic_handle_irq(msi_irq); - else - dev_info(dev, "unhandled MSI\n"); - } else { - /* Unknown MSI, just clear it */ - dev_dbg(dev, "unexpected MSI\n"); - } - - /* see if there's any more pending in this vector */ - reg = rcar_pci_read_reg(pcie, PCIEMSIFR); - } - - return IRQ_HANDLED; -} - -static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, - struct msi_desc *desc) -{ - struct rcar_msi *msi = to_rcar_msi(chip); - struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip); - struct msi_msg msg; - unsigned int irq; - int hwirq; - - hwirq = rcar_msi_alloc(msi); - if (hwirq < 0) - return hwirq; - - irq = irq_find_mapping(msi->domain, hwirq); - if (!irq) { - rcar_msi_free(msi, hwirq); - return -EINVAL; - } - - irq_set_msi_desc(irq, desc); - - msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; - msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); - msg.data = hwirq; - - pci_write_msi_msg(irq, &msg); - - return 0; -} - -static int rcar_msi_setup_irqs(struct msi_controller *chip, - struct pci_dev *pdev, int nvec, int type) -{ - struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip); - struct rcar_msi *msi = to_rcar_msi(chip); - struct msi_desc *desc; - struct msi_msg msg; - unsigned int irq; - int hwirq; - int i; - - /* MSI-X interrupts are not supported */ - if (type == PCI_CAP_ID_MSIX) - return -EINVAL; - - WARN_ON(!list_is_singular(&pdev->dev.msi_list)); - desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list); - - hwirq = rcar_msi_alloc_region(msi, nvec); - if (hwirq < 0) - return -ENOSPC; - - irq = irq_find_mapping(msi->domain, hwirq); - if (!irq) - return -ENOSPC; - - for (i = 0; i < nvec; i++) { - /* - * irq_create_mapping() called from rcar_pcie_probe() pre- - * allocates descs, so there is no need to allocate descs here. - * We can therefore assume that if irq_find_mapping() above - * returns non-zero, then the descs are also successfully - * allocated. - */ - if (irq_set_msi_desc_off(irq, i, desc)) { - /* TODO: clear */ - return -EINVAL; - } - } - - desc->nvec_used = nvec; - desc->msi_attrib.multiple = order_base_2(nvec); - - msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; - msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); - msg.data = hwirq; - - pci_write_msi_msg(irq, &msg); - - return 0; -} - -static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) -{ - struct rcar_msi *msi = to_rcar_msi(chip); - struct irq_data *d = irq_get_irq_data(irq); - - rcar_msi_free(msi, d->hwirq); -} - -static struct irq_chip rcar_msi_irq_chip = { - .name = "R-Car PCIe MSI", - .irq_enable = pci_msi_unmask_irq, - .irq_disable = pci_msi_mask_irq, - .irq_mask = pci_msi_mask_irq, - .irq_unmask = pci_msi_unmask_irq, -}; - -static int rcar_msi_map(struct irq_domain *domain, unsigned int irq, - irq_hw_number_t hwirq) -{ - irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq); - irq_set_chip_data(irq, domain->host_data); - - return 0; -} - -static const struct irq_domain_ops msi_domain_ops = { - .map = rcar_msi_map, -}; - -static void rcar_pcie_unmap_msi(struct rcar_pcie *pcie) -{ - struct rcar_msi *msi = &pcie->msi; - int i, irq; - - for (i = 0; i < INT_PCI_MSI_NR; i++) { - irq = irq_find_mapping(msi->domain, i); - if (irq > 0) - irq_dispose_mapping(irq); - } - - irq_domain_remove(msi->domain); -} - -static int rcar_pcie_enable_msi(struct rcar_pcie *pcie) -{ - struct device *dev = pcie->dev; - struct rcar_msi *msi = &pcie->msi; - phys_addr_t base; - int err, i; - - mutex_init(&msi->lock); - - msi->chip.dev = dev; - msi->chip.setup_irq = rcar_msi_setup_irq; - msi->chip.setup_irqs = rcar_msi_setup_irqs; - msi->chip.teardown_irq = rcar_msi_teardown_irq; - - msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR, - &msi_domain_ops, &msi->chip); - if (!msi->domain) { - dev_err(dev, "failed to create IRQ domain\n"); - return -ENOMEM; - } - - for (i = 0; i < INT_PCI_MSI_NR; i++) - irq_create_mapping(msi->domain, i); - - /* Two irqs are for MSI, but they are also used for non-MSI irqs */ - err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq, - IRQF_SHARED | IRQF_NO_THREAD, - rcar_msi_irq_chip.name, pcie); - if (err < 0) { - dev_err(dev, "failed to request IRQ: %d\n", err); - goto err; - } - - err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq, - IRQF_SHARED | IRQF_NO_THREAD, - rcar_msi_irq_chip.name, pcie); - if (err < 0) { - dev_err(dev, "failed to request IRQ: %d\n", err); - goto err; - } - - /* setup MSI data target */ - msi->pages = __get_free_pages(GFP_KERNEL, 0); - if (!msi->pages) { - err = -ENOMEM; - goto err; - } - base = virt_to_phys((void *)msi->pages); - - rcar_pci_write_reg(pcie, lower_32_bits(base) | MSIFE, PCIEMSIALR); - rcar_pci_write_reg(pcie, upper_32_bits(base), PCIEMSIAUR); - - /* enable all MSI interrupts */ - rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER); - - return 0; - -err: - rcar_pcie_unmap_msi(pcie); - return err; -} - -static void rcar_pcie_teardown_msi(struct rcar_pcie *pcie) -{ - struct rcar_msi *msi = &pcie->msi; - - /* Disable all MSI interrupts */ - rcar_pci_write_reg(pcie, 0, PCIEMSIIER); - - /* Disable address decoding of the MSI interrupt, MSIFE */ - rcar_pci_write_reg(pcie, 0, PCIEMSIALR); - - free_pages(msi->pages, 0); - - rcar_pcie_unmap_msi(pcie); -} - -static int rcar_pcie_get_resources(struct rcar_pcie *pcie) -{ - struct device *dev = pcie->dev; - struct resource res; - int err, i; - - pcie->phy = devm_phy_optional_get(dev, "pcie"); - if (IS_ERR(pcie->phy)) - return PTR_ERR(pcie->phy); - - err = of_address_to_resource(dev->of_node, 0, &res); - if (err) - return err; - - pcie->base = devm_ioremap_resource(dev, &res); - if (IS_ERR(pcie->base)) - return PTR_ERR(pcie->base); - - pcie->bus_clk = devm_clk_get(dev, "pcie_bus"); - if (IS_ERR(pcie->bus_clk)) { - dev_err(dev, "cannot get pcie bus clock\n"); - return PTR_ERR(pcie->bus_clk); - } - - i = irq_of_parse_and_map(dev->of_node, 0); - if (!i) { - dev_err(dev, "cannot get platform resources for msi interrupt\n"); - err = -ENOENT; - goto err_irq1; - } - pcie->msi.irq1 = i; - - i = irq_of_parse_and_map(dev->of_node, 1); - if (!i) { - dev_err(dev, "cannot get platform resources for msi interrupt\n"); - err = -ENOENT; - goto err_irq2; - } - pcie->msi.irq2 = i; - - return 0; - -err_irq2: - irq_dispose_mapping(pcie->msi.irq1); -err_irq1: - return err; -} - -static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, - struct of_pci_range *range, - int *index) +void rcar_pcie_set_inbound(void __iomem *base, + u64 cpu_addr, u64 pci_addr, + u64 mask, int idx, bool host) { - u64 restype = range->flags; - u64 cpu_addr = range->cpu_addr; - u64 cpu_end = range->cpu_addr + range->size; - u64 pci_addr = range->pci_addr; - u32 flags = LAM_64BIT | LAR_ENABLE; - u64 mask; - u64 size; - int idx = *index; - - if (restype & IORESOURCE_PREFETCH) - flags |= LAM_PREFETCH; - /* - * If the size of the range is larger than the alignment of the start - * address, we have to use multiple entries to perform the mapping. - */ - if (cpu_addr > 0) { - unsigned long nr_zeros = __ffs64(cpu_addr); - u64 alignment = 1ULL << nr_zeros; - - size = min(range->size, alignment); - } else { - size = range->size; - } - /* Hardware supports max 4GiB inbound region */ - size = min(size, 1ULL << 32); - - mask = roundup_pow_of_two(size) - 1; - mask &= ~0xf; - - while (cpu_addr < cpu_end) { - /* - * Set up 64-bit inbound regions as the range parser doesn't - * distinguish between 32 and 64-bit types. - */ - rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), + * Set up 64-bit inbound regions as the range parser doesn't + * distinguish between 32 and 64-bit types. + */ + if (host) { + rcar_pci_write_reg(base, lower_32_bits(pci_addr), PCIEPRAR(idx)); - rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx)); - rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, - PCIELAMR(idx)); - - rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), + rcar_pci_write_reg(base, upper_32_bits(pci_addr), PCIEPRAR(idx + 1)); - rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), - PCIELAR(idx + 1)); - rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1)); - - pci_addr += size; - cpu_addr += size; - idx += 2; - - if (idx > MAX_NR_INBOUND_MAPS) { - dev_err(pcie->dev, "Failed to map inbound regions!\n"); - return -EINVAL; - } } - *index = idx; - - return 0; -} -static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie, - struct device_node *np) -{ - struct of_pci_range range; - struct of_pci_range_parser parser; - int index = 0; - int err; - - if (of_pci_dma_range_parser_init(&parser, np)) - return -EINVAL; - - /* Get the dma-ranges from DT */ - for_each_of_pci_range(&parser, &range) { - u64 end = range.cpu_addr + range.size - 1; + rcar_pci_write_reg(base, lower_32_bits(cpu_addr), PCIELAR(idx)); + rcar_pci_write_reg(base, lower_32_bits(mask), PCIELAMR(idx)); - dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", - range.flags, range.cpu_addr, end, range.pci_addr); - - err = rcar_pcie_inbound_ranges(pcie, &range, &index); - if (err) - return err; - } + rcar_pci_write_reg(base, upper_32_bits(cpu_addr), PCIELAR(idx + 1)); + rcar_pci_write_reg(base, 0, PCIELAMR(idx + 1)); - return 0; -} - -static const struct of_device_id rcar_pcie_of_match[] = { - { .compatible = "renesas,pcie-r8a7779", - .data = rcar_pcie_phy_init_h1 }, - { .compatible = "renesas,pcie-r8a7790", - .data = rcar_pcie_phy_init_gen2 }, - { .compatible = "renesas,pcie-r8a7791", - .data = rcar_pcie_phy_init_gen2 }, - { .compatible = "renesas,pcie-rcar-gen2", - .data = rcar_pcie_phy_init_gen2 }, - { .compatible = "renesas,pcie-r8a7795", - .data = rcar_pcie_phy_init_gen3 }, - { .compatible = "renesas,pcie-rcar-gen3", - .data = rcar_pcie_phy_init_gen3 }, - {}, -}; - -static int rcar_pcie_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct rcar_pcie *pcie; - u32 data; - int err; - int (*phy_init_fn)(struct rcar_pcie *); - struct pci_host_bridge *bridge; - - bridge = pci_alloc_host_bridge(sizeof(*pcie)); - if (!bridge) - return -ENOMEM; - - pcie = pci_host_bridge_priv(bridge); - - pcie->dev = dev; - platform_set_drvdata(pdev, pcie); - - err = pci_parse_request_of_pci_ranges(dev, &pcie->resources, NULL); - if (err) - goto err_free_bridge; - - pm_runtime_enable(pcie->dev); - err = pm_runtime_get_sync(pcie->dev); - if (err < 0) { - dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); - goto err_pm_disable; - } - - err = rcar_pcie_get_resources(pcie); - if (err < 0) { - dev_err(dev, "failed to request resources: %d\n", err); - goto err_pm_put; - } - - err = clk_prepare_enable(pcie->bus_clk); - if (err) { - dev_err(dev, "failed to enable bus clock: %d\n", err); - goto err_unmap_msi_irqs; - } - - err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node); - if (err) - goto err_clk_disable; - - phy_init_fn = of_device_get_match_data(dev); - err = phy_init_fn(pcie); - if (err) { - dev_err(dev, "failed to init PCIe PHY\n"); - goto err_clk_disable; - } - - /* Failure to get a link might just be that no cards are inserted */ - if (rcar_pcie_hw_init(pcie)) { - dev_info(dev, "PCIe link down\n"); - err = -ENODEV; - goto err_phy_shutdown; - } - - data = rcar_pci_read_reg(pcie, MACSR); - dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); - - if (IS_ENABLED(CONFIG_PCI_MSI)) { - err = rcar_pcie_enable_msi(pcie); - if (err < 0) { - dev_err(dev, - "failed to enable MSI support: %d\n", - err); - goto err_phy_shutdown; - } - } - - err = rcar_pcie_enable(pcie); - if (err) - goto err_msi_teardown; - - return 0; - -err_msi_teardown: - if (IS_ENABLED(CONFIG_PCI_MSI)) - rcar_pcie_teardown_msi(pcie); - -err_phy_shutdown: - if (pcie->phy) { - phy_power_off(pcie->phy); - phy_exit(pcie->phy); - } - -err_clk_disable: - clk_disable_unprepare(pcie->bus_clk); - -err_unmap_msi_irqs: - irq_dispose_mapping(pcie->msi.irq2); - irq_dispose_mapping(pcie->msi.irq1); - -err_pm_put: - pm_runtime_put(dev); - -err_pm_disable: - pm_runtime_disable(dev); - pci_free_resource_list(&pcie->resources); - -err_free_bridge: - pci_free_host_bridge(bridge); - - return err; -} - -static int rcar_pcie_resume_noirq(struct device *dev) -{ - struct rcar_pcie *pcie = dev_get_drvdata(dev); - - if (rcar_pci_read_reg(pcie, PMSR) && - !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) - return 0; - - /* Re-establish the PCIe link */ - rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); - return rcar_pcie_wait_for_dl(pcie); + /* flush modifications */ + wmb(); } - -static const struct dev_pm_ops rcar_pcie_pm_ops = { - .resume_noirq = rcar_pcie_resume_noirq, -}; - -static struct platform_driver rcar_pcie_driver = { - .driver = { - .name = "rcar-pcie", - .of_match_table = rcar_pcie_of_match, - .pm = &rcar_pcie_pm_ops, - .suppress_bind_attrs = true, - }, - .probe = rcar_pcie_probe, -}; -builtin_platform_driver(rcar_pcie_driver); diff --git a/drivers/pci/controller/pcie-rcar.h b/drivers/pci/controller/pcie-rcar.h new file mode 100644 index 0000000..502621d --- /dev/null +++ b/drivers/pci/controller/pcie-rcar.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * PCIe driver for Renesas R-Car SoCs + * Copyright (C) 2014-2019 Renesas Electronics Europe Ltd + * + * Author: Phil Edworthy <phil.edworthy@renesas.com> + */ +#ifndef _PCIE_RCAR_H +#define _PCIE_RCAR_H + +#define PCIECAR 0x000010 +#define PCIECCTLR 0x000018 +#define CONFIG_SEND_ENABLE BIT(31) +#define TYPE0 (0 << 8) +#define TYPE1 BIT(8) +#define PCIECDR 0x000020 +#define PCIEMSR 0x000028 +#define PCIEINTXR 0x000400 +#define PCIEPHYSR 0x0007f0 +#define PHYRDY BIT(0) +#define PCIEMSITXR 0x000840 + +/* Transfer control */ +#define PCIETCTLR 0x02000 +#define DL_DOWN BIT(3) +#define CFINIT BIT(0) +#define PCIETSTR 0x02004 +#define DATA_LINK_ACTIVE BIT(0) +#define PCIEERRFR 0x02020 +#define UNSUPPORTED_REQUEST BIT(4) +#define PCIEMSIFR 0x02044 +#define PCIEMSIALR 0x02048 +#define MSIFE BIT(0) +#define PCIEMSIAUR 0x0204c +#define PCIEMSIIER 0x02050 + +/* root port address */ +#define PCIEPRAR(x) (0x02080 + ((x) * 0x4)) + +/* local address reg & mask */ +#define PCIELAR(x) (0x02200 + ((x) * 0x20)) +#define PCIELAMR(x) (0x02208 + ((x) * 0x20)) +#define LAM_PREFETCH BIT(3) +#define LAM_64BIT BIT(2) +#define LAR_ENABLE BIT(1) + +/* PCIe address reg & mask */ +#define PCIEPALR(x) (0x03400 + ((x) * 0x20)) +#define PCIEPAUR(x) (0x03404 + ((x) * 0x20)) +#define PCIEPAMR(x) (0x03408 + ((x) * 0x20)) +#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20)) +#define PAR_ENABLE BIT(31) +#define IO_SPACE BIT(8) + +/* Configuration */ +#define PCICONF(x) (0x010000 + ((x) * 0x4)) +#define PMCAP(x) (0x010040 + ((x) * 0x4)) +#define EXPCAP(x) (0x010070 + ((x) * 0x4)) +#define VCCAP(x) (0x010100 + ((x) * 0x4)) + +/* link layer */ +#define IDSETR0 0x011000 +#define DEVICE_ID_SHFIT 16 +#define IDSETR1 0x011004 +#define SUBIDSETR 0x011024 +#define TLCTLR 0x011048 +#define MACSR 0x011054 +#define SPCHGFIN BIT(4) +#define SPCHGFAIL BIT(6) +#define SPCHGSUC BIT(7) +#define LINK_SPEED (0xf << 16) +#define LINK_SPEED_2_5GTS BIT(16) +#define LINK_SPEED_5_0GTS BIT(17) +#define MACCTLR 0x011058 +#define MACCTLR_RESERVED BIT(0) +#define SPEED_CHANGE BIT(24) +#define SCRAMBLE_DISABLE BIT(27) +#define PMSR 0x01105c +#define MACS2R 0x011078 +#define MACCGSPSETR 0x011084 +#define SPCNGRSN BIT(31) + +/* R-Car H1 PHY */ +#define H1_PCIEPHYADRR 0x04000c +#define WRITE_CMD BIT(16) +#define PHY_ACK BIT(24) +#define RATE_POS 12 +#define LANE_POS 8 +#define ADR_POS 0 +#define H1_PCIEPHYDOUTR 0x040014 + +/* R-Car Gen2 PHY */ +#define GEN2_PCIEPHYADDR 0x780 +#define GEN2_PCIEPHYDATA 0x784 +#define GEN2_PCIEPHYCTRL 0x78c + +#define INT_PCI_MSI_NR 32 + +#define RCONF(x) (PCICONF(0) + (x)) +#define RPMCAP(x) (PMCAP(0) + (x)) +#define REXPCAP(x) (EXPCAP(0) + (x)) +#define RVCCAP(x) (VCCAP(0) + (x)) + +#define INTDIS_SHIFT BIT(10) +#define ASTINTX_SHIFT BIT(16) + +#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24) +#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19) +#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16) + +#define RCAR_PCI_MAX_RESOURCES 4 +#define MAX_NR_INBOUND_MAPS 6 + +enum { + RCAR_PCI_ACCESS_READ, + RCAR_PCI_ACCESS_WRITE, +}; + +void rcar_pci_write_reg(void __iomem *base, u32 val, unsigned int reg); +u32 rcar_pci_read_reg(void __iomem *base, unsigned int reg); +void rcar_rmw32(void __iomem *base, int where, u32 mask, u32 data); +int rcar_pcie_wait_for_phyrdy(void __iomem *base); +int rcar_pcie_wait_for_dl(void __iomem *base); +void rcar_pcie_set_outbound(int win, void __iomem *base, + struct resource *res, bool host); +void rcar_pcie_set_inbound(void __iomem *base, u64 cpu_addr, u64 pci_addr, + u64 mask, int idx, bool host); + +#endif -- 2.7.4 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [v2 1/6] pci: pcie-rcar: preparation for adding endpoint support 2019-12-13 8:47 ` [v2 1/6] pci: pcie-rcar: preparation for adding endpoint support Lad Prabhakar @ 2019-12-13 21:06 ` Bjorn Helgaas 2019-12-16 7:52 ` Lad, Prabhakar 0 siblings, 1 reply; 27+ messages in thread From: Bjorn Helgaas @ 2019-12-13 21:06 UTC (permalink / raw) To: Lad Prabhakar Cc: Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel, linux-arm-kernel, linux-renesas-soc, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar On Fri, Dec 13, 2019 at 08:47:43AM +0000, Lad Prabhakar wrote: > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > this patch prepares for adding endpoint support to rcar controller, > there are no functional changes with this patch, a common file is > created so that it can be shared with endpoint driver. Alongside > this patch fixes checkpatch reported issues. Can you please split this into: - a patch that moves code only, with no other changes except any necessary Kconfig and Makefile changes - another patch that fixes the checkpatch things When the checkpatch fixes are buried in the code move, it's impossible to review them. > Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > arch/arm64/configs/defconfig | 2 +- > drivers/pci/controller/Kconfig | 4 +- > drivers/pci/controller/Makefile | 2 +- > drivers/pci/controller/pcie-rcar-host.c | 1056 ++++++++++++++++++++++++++ > drivers/pci/controller/pcie-rcar.c | 1229 ++----------------------------- > drivers/pci/controller/pcie-rcar.h | 129 ++++ > 6 files changed, 1242 insertions(+), 1180 deletions(-) > create mode 100644 drivers/pci/controller/pcie-rcar-host.c > create mode 100644 drivers/pci/controller/pcie-rcar.h ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 1/6] pci: pcie-rcar: preparation for adding endpoint support 2019-12-13 21:06 ` Bjorn Helgaas @ 2019-12-16 7:52 ` Lad, Prabhakar 0 siblings, 0 replies; 27+ messages in thread From: Lad, Prabhakar @ 2019-12-16 7:52 UTC (permalink / raw) To: Bjorn Helgaas Cc: Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML, LAK, Linux-Renesas, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar Hi Bjorn, On Fri, Dec 13, 2019 at 9:06 PM Bjorn Helgaas <helgaas@kernel.org> wrote: > > On Fri, Dec 13, 2019 at 08:47:43AM +0000, Lad Prabhakar wrote: > > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > this patch prepares for adding endpoint support to rcar controller, > > there are no functional changes with this patch, a common file is > > created so that it can be shared with endpoint driver. Alongside > > this patch fixes checkpatch reported issues. > > Can you please split this into: > > - a patch that moves code only, with no other changes except any > necessary Kconfig and Makefile changes > - another patch that fixes the checkpatch things > > When the checkpatch fixes are buried in the code move, it's impossible > to review them. > thank you for the review.sure I'll split up the patches and resend. Cheers, --Prabhakar > > Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > arch/arm64/configs/defconfig | 2 +- > > drivers/pci/controller/Kconfig | 4 +- > > drivers/pci/controller/Makefile | 2 +- > > drivers/pci/controller/pcie-rcar-host.c | 1056 ++++++++++++++++++++++++++ > > drivers/pci/controller/pcie-rcar.c | 1229 ++----------------------------- > > drivers/pci/controller/pcie-rcar.h | 129 ++++ > > 6 files changed, 1242 insertions(+), 1180 deletions(-) > > create mode 100644 drivers/pci/controller/pcie-rcar-host.c > > create mode 100644 drivers/pci/controller/pcie-rcar.h ^ permalink raw reply [flat|nested] 27+ messages in thread
* [v2 2/6] pci: endpoint: add support to handle features of outbound memory 2019-12-13 8:47 [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs Lad Prabhakar 2019-12-13 8:47 ` [v2 1/6] pci: pcie-rcar: preparation for adding endpoint support Lad Prabhakar @ 2019-12-13 8:47 ` Lad Prabhakar 2019-12-13 21:06 ` Bjorn Helgaas 2019-12-16 11:35 ` Kishon Vijay Abraham I 2019-12-13 8:47 ` [v2 3/6] of: address: add support to parse PCI outbound-ranges Lad Prabhakar ` (4 subsequent siblings) 6 siblings, 2 replies; 27+ messages in thread From: Lad Prabhakar @ 2019-12-13 8:47 UTC (permalink / raw) To: Bjorn Helgaas, Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci Cc: Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel, linux-arm-kernel, linux-renesas-soc, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> rcar pcie controller has support to map multiple memory regions for mapping the outbound memory in local system, this feature inspires to add support for handling such features in endpoint framework. similar features exists on other controllers where outbound regions can be specifically used for low/high priority transactions, and regions can be flagged and used for allocation of large/small memory allocations. This patch adds support to handle such features, where the properties described for outbound regions are used whenever a request to memory is made. Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/pci/controller/dwc/pcie-designware-ep.c | 30 ++-- drivers/pci/controller/pcie-cadence-ep.c | 11 +- drivers/pci/controller/pcie-rockchip-ep.c | 13 +- drivers/pci/endpoint/functions/pci-epf-test.c | 47 ++++-- drivers/pci/endpoint/pci-epc-core.c | 7 +- drivers/pci/endpoint/pci-epc-mem.c | 216 +++++++++++++++++++----- include/linux/pci-epc.h | 72 ++++++-- 7 files changed, 307 insertions(+), 89 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 3dd2e26..be6aa94 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -195,7 +195,7 @@ static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no, } static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, - phys_addr_t addr, + phys_addr_t addr, int window, u64 pci_addr, size_t size) { int ret; @@ -367,6 +367,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, unsigned int aligned_offset; u16 msg_ctrl, msg_data; u32 msg_addr_lower, msg_addr_upper, reg; + int window = PCI_EPC_DEFAULT_WINDOW; u64 msg_addr; bool has_upper; int ret; @@ -390,11 +391,11 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, reg = ep->msi_cap + PCI_MSI_DATA_32; msg_data = dw_pcie_readw_dbi(pci, reg); } - aligned_offset = msg_addr_lower & (epc->mem->page_size - 1); + aligned_offset = msg_addr_lower & (epc->mem[window]->page_size - 1); msg_addr = ((u64)msg_addr_upper) << 32 | (msg_addr_lower & ~aligned_offset); - ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, - epc->mem->page_size); + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, window, + msg_addr, epc->mem[window]->page_size); if (ret) return ret; @@ -416,6 +417,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, u32 reg, msg_data, vec_ctrl; u64 tbl_addr, msg_addr, reg_u64; void __iomem *msix_tbl; + int window = PCI_EPC_DEFAULT_WINDOW; int ret; reg = ep->msix_cap + PCI_MSIX_TABLE; @@ -452,8 +454,8 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, return -EPERM; } - ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, - epc->mem->page_size); + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, window, + msg_addr, epc->mem[window]->page_size); if (ret) return ret; @@ -466,10 +468,11 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, void dw_pcie_ep_exit(struct dw_pcie_ep *ep) { + int window = PCI_EPC_DEFAULT_WINDOW; struct pci_epc *epc = ep->epc; pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, - epc->mem->page_size); + epc->mem[window]->page_size); pci_epc_mem_exit(epc); } @@ -499,9 +502,12 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) u32 reg; void *addr; u8 hdr_type; + int window; unsigned int nbars; unsigned int offset; struct pci_epc *epc; + size_t msi_page_size; + struct pci_epc_mem_window mem_window; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct device *dev = pci->dev; struct device_node *np = dev->of_node; @@ -574,15 +580,17 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (ret < 0) epc->max_functions = 1; - ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, - ep->page_size); + mem_window.phys_base = ep->phys_base; + mem_window.size = ep->addr_size; + ret = __pci_epc_mem_init(epc, &mem_window, 1, ep->page_size); if (ret < 0) { dev_err(dev, "Failed to initialize address space\n"); return ret; } - ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, - epc->mem->page_size); + msi_page_size = epc->mem[PCI_EPC_DEFAULT_WINDOW]->page_size; + ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, &window, + msi_page_size, 0x0); if (!ep->msi_mem) { dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); return -ENOMEM; diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c index def7820..2410706 100644 --- a/drivers/pci/controller/pcie-cadence-ep.c +++ b/drivers/pci/controller/pcie-cadence-ep.c @@ -172,7 +172,7 @@ static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, } static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr, - u64 pci_addr, size_t size) + int window, u64 pci_addr, size_t size) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; @@ -434,12 +434,14 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; + struct pci_epc_mem_window mem_window; struct cdns_pcie_ep *ep; struct cdns_pcie *pcie; struct pci_epc *epc; struct resource *res; int ret; int phy_count; + int window; ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); if (!ep) @@ -502,15 +504,16 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) epc->max_functions = 1; - ret = pci_epc_mem_init(epc, pcie->mem_res->start, - resource_size(pcie->mem_res)); + mem_window.phys_base = pcie->mem_res->start; + mem_window.size = resource_size(pcie->mem_res); + ret = pci_epc_mem_init(epc, &mem_window, 1); if (ret < 0) { dev_err(dev, "failed to initialize the memory space\n"); goto err_init; } ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, - SZ_128K); + &window, SZ_128K, 0x0); if (!ep->irq_cpu_addr) { dev_err(dev, "failed to reserve memory space for MSI\n"); ret = -ENOMEM; diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index d743b0a..828052c 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -256,8 +256,8 @@ static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, } static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, - phys_addr_t addr, u64 pci_addr, - size_t size) + phys_addr_t addr, int window, + u64 pci_addr, size_t size) { struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *pcie = &ep->rockchip; @@ -562,11 +562,13 @@ static const struct of_device_id rockchip_pcie_ep_of_match[] = { static int rockchip_pcie_ep_probe(struct platform_device *pdev) { + struct pci_epc_mem_window mem_window; struct device *dev = &pdev->dev; struct rockchip_pcie_ep *ep; struct rockchip_pcie *rockchip; struct pci_epc *epc; size_t max_regions; + int window; int err; ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); @@ -614,15 +616,16 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) /* Only enable function 0 by default */ rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); - err = pci_epc_mem_init(epc, rockchip->mem_res->start, - resource_size(rockchip->mem_res)); + mem_window.phys_base = rockchip->mem_res->start; + mem_window.size = resource_size(rockchip->mem_res); + err = pci_epc_mem_init(epc, &mem_window, 1); if (err < 0) { dev_err(dev, "failed to initialize the memory space\n"); goto err_uninit_port; } ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, - SZ_128K); + &window, SZ_128K, 0x0); if (!ep->irq_cpu_addr) { dev_err(dev, "failed to reserve memory space for MSI\n"); err = -ENOMEM; diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index 1cfe368..4768d54 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -84,8 +84,14 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) struct pci_epc *epc = epf->epc; enum pci_barno test_reg_bar = epf_test->test_reg_bar; struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; - - src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size); + int window; + + src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, + &window, reg->size, + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); if (!src_addr) { dev_err(dev, "Failed to allocate source address\n"); reg->status = STATUS_SRC_ADDR_INVALID; @@ -93,15 +99,20 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) goto err; } - ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, reg->src_addr, - reg->size); + ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, window, + reg->src_addr, reg->size); if (ret) { dev_err(dev, "Failed to map source address\n"); reg->status = STATUS_SRC_ADDR_INVALID; goto err_src_addr; } - dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size); + dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, + &window, reg->size, + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); if (!dst_addr) { dev_err(dev, "Failed to allocate destination address\n"); reg->status = STATUS_DST_ADDR_INVALID; @@ -109,8 +120,8 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) goto err_src_map_addr; } - ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, reg->dst_addr, - reg->size); + ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, window, + reg->dst_addr, reg->size); if (ret) { dev_err(dev, "Failed to map destination address\n"); reg->status = STATUS_DST_ADDR_INVALID; @@ -146,8 +157,13 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test) struct pci_epc *epc = epf->epc; enum pci_barno test_reg_bar = epf_test->test_reg_bar; struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; + int window; - src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); + src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, &window, reg->size, + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); if (!src_addr) { dev_err(dev, "Failed to allocate address\n"); reg->status = STATUS_SRC_ADDR_INVALID; @@ -155,8 +171,8 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test) goto err; } - ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->src_addr, - reg->size); + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, window, + reg->src_addr, reg->size); if (ret) { dev_err(dev, "Failed to map address\n"); reg->status = STATUS_SRC_ADDR_INVALID; @@ -193,13 +209,18 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test) void __iomem *dst_addr; void *buf; phys_addr_t phys_addr; + int window; struct pci_epf *epf = epf_test->epf; struct device *dev = &epf->dev; struct pci_epc *epc = epf->epc; enum pci_barno test_reg_bar = epf_test->test_reg_bar; struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; - dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); + dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, &window, reg->size, + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); if (!dst_addr) { dev_err(dev, "Failed to allocate address\n"); reg->status = STATUS_DST_ADDR_INVALID; @@ -207,8 +228,8 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test) goto err; } - ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->dst_addr, - reg->size); + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, window, + reg->dst_addr, reg->size); if (ret) { dev_err(dev, "Failed to map address\n"); reg->status = STATUS_DST_ADDR_INVALID; diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 2091508..289c266 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -358,13 +358,15 @@ EXPORT_SYMBOL_GPL(pci_epc_unmap_addr); * @epc: the EPC device on which address is allocated * @func_no: the endpoint function number in the EPC device * @phys_addr: physical address of the local system + * @window: index to the window region where PCI address will be mapped * @pci_addr: PCI address to which the physical address should be mapped * @size: the size of the allocation * * Invoke to map CPU address with PCI address. */ int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, - phys_addr_t phys_addr, u64 pci_addr, size_t size) + phys_addr_t phys_addr, int window, + u64 pci_addr, size_t size) { int ret; unsigned long flags; @@ -376,7 +378,8 @@ int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, return 0; spin_lock_irqsave(&epc->lock, flags); - ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size); + ret = epc->ops->map_addr(epc, func_no, phys_addr, + window, pci_addr, size); spin_unlock_irqrestore(&epc->lock, flags); return ret; diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c index 2bf8bd1..4b610cd 100644 --- a/drivers/pci/endpoint/pci-epc-mem.c +++ b/drivers/pci/endpoint/pci-epc-mem.c @@ -39,56 +39,78 @@ static int pci_epc_mem_get_order(struct pci_epc_mem *mem, size_t size) * __pci_epc_mem_init() - initialize the pci_epc_mem structure * @epc: the EPC device that invoked pci_epc_mem_init * @phys_base: the physical address of the base - * @size: the size of the address space + * @num_windows: number of windows device supports * @page_size: size of each page * * Invoke to initialize the pci_epc_mem structure used by the * endpoint functions to allocate mapped PCI address. */ -int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_base, size_t size, - size_t page_size) +int __pci_epc_mem_init(struct pci_epc *epc, struct pci_epc_mem_window *windows, + int num_windows, size_t page_size) { - int ret; - struct pci_epc_mem *mem; - unsigned long *bitmap; + struct pci_epc_mem *mem = NULL; + unsigned long *bitmap = NULL; unsigned int page_shift; - int pages; int bitmap_size; + int pages; + int ret; + int i; + + epc->mem_windows = 0; + + if (!windows) + return -EINVAL; + + if (num_windows <= 0) + return -EINVAL; if (page_size < PAGE_SIZE) page_size = PAGE_SIZE; page_shift = ilog2(page_size); - pages = size >> page_shift; - bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); - mem = kzalloc(sizeof(*mem), GFP_KERNEL); - if (!mem) { - ret = -ENOMEM; - goto err; - } + epc->mem = kcalloc(num_windows, sizeof(*mem), GFP_KERNEL); + if (!epc->mem) + return -EINVAL; - bitmap = kzalloc(bitmap_size, GFP_KERNEL); - if (!bitmap) { - ret = -ENOMEM; - goto err_mem; - } + for (i = 0; i < num_windows; i++) { + pages = windows[i].phys_base >> page_shift; + bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); - mem->bitmap = bitmap; - mem->phys_base = phys_base; - mem->page_size = page_size; - mem->pages = pages; - mem->size = size; + mem = kzalloc(sizeof(*mem), GFP_KERNEL); + if (!mem) { + ret = -ENOMEM; + goto err_mem; + } - epc->mem = mem; + bitmap = kzalloc(bitmap_size, GFP_KERNEL); + if (!bitmap) { + ret = -ENOMEM; + goto err_mem; + } + + mem->bitmap = bitmap; + mem->window.phys_base = windows[i].phys_base; + mem->page_size = page_size; + mem->pages = pages; + mem->window.size = windows[i].size; + mem->window.map_size = 0; + mem->window.flags = windows[i].flags; + + epc->mem[i] = mem; + } + epc->mem_windows = num_windows; return 0; err_mem: - kfree(mem); + for (; i >= 0; i--) { + kfree(mem->bitmap); + kfree(epc->mem[i]); + } + kfree(epc->mem); -err: -return ret; + return ret; } EXPORT_SYMBOL_GPL(__pci_epc_mem_init); @@ -101,48 +123,152 @@ EXPORT_SYMBOL_GPL(__pci_epc_mem_init); */ void pci_epc_mem_exit(struct pci_epc *epc) { - struct pci_epc_mem *mem = epc->mem; + struct pci_epc_mem *mem; + int i; + + if (!epc->mem_windows) + return; + + for (i = 0; i <= epc->mem_windows; i--) { + mem = epc->mem[i]; + kfree(mem->bitmap); + kfree(epc->mem[i]); + } + kfree(epc->mem); epc->mem = NULL; - kfree(mem->bitmap); - kfree(mem); + epc->mem_windows = 0; } EXPORT_SYMBOL_GPL(pci_epc_mem_exit); +static int pci_epc_find_best_fit_window(struct pci_epc *epc, size_t size, + u32 flags) +{ + size_t window_least_size = 0; + int best_fit_window = -1; + struct pci_epc_mem *mem; + size_t actual_size; + size_t avail_size; + u32 win_flags; + int i; + + for (i = 0; i < epc->mem_windows; i++) { + mem = epc->mem[i]; + win_flags = mem->window.flags; + + actual_size = ALIGN(size, mem->page_size); + avail_size = mem->window.size - mem->window.map_size; + + if (win_flags == 0x0) { + if (best_fit_window == -1) { + if (actual_size <= avail_size) { + best_fit_window = i; + window_least_size = mem->window.size; + } + } else { + if (actual_size <= avail_size && + mem->window.size < window_least_size) { + best_fit_window = i; + window_least_size = mem->window.size; + } + } + } else { + if (mem->window.map_size && + (win_flags | PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC)) + continue; + + if (!(win_flags | flags)) + continue; + + if (best_fit_window == -1) { + if (actual_size <= avail_size) { + best_fit_window = i; + window_least_size = mem->window.size; + } + } else { + if (actual_size <= avail_size && + mem->window.size < window_least_size) { + best_fit_window = i; + window_least_size = mem->window.size; + } + } + } + } + + return best_fit_window; +} + /** * pci_epc_mem_alloc_addr() - allocate memory address from EPC addr space * @epc: the EPC device on which memory has to be allocated * @phys_addr: populate the allocated physical address here + * @window: populate the window here which will be used to map PCI address * @size: the size of the address space that has to be allocated + * @flags: look for window as requested in flags * * Invoke to allocate memory address from the EPC address space. This * is usually done to map the remote RC address into the local system. */ void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, - phys_addr_t *phys_addr, size_t size) + phys_addr_t *phys_addr, + int *window, size_t size, uint32_t flags) { + int best_fit = PCI_EPC_DEFAULT_WINDOW; + void __iomem *virt_addr = NULL; + struct pci_epc_mem *mem; + unsigned int page_shift; int pageno; - void __iomem *virt_addr; - struct pci_epc_mem *mem = epc->mem; - unsigned int page_shift = ilog2(mem->page_size); int order; + if (epc->mem_windows <= 0) + return NULL; + + if (epc->mem_windows > 1) { + best_fit = pci_epc_find_best_fit_window(epc, size, flags); + if (best_fit < 0) + return NULL; + } + + mem = epc->mem[best_fit]; size = ALIGN(size, mem->page_size); + if (size > (mem->window.size - mem->window.map_size)) + return NULL; + page_shift = ilog2(mem->page_size); order = pci_epc_mem_get_order(mem, size); pageno = bitmap_find_free_region(mem->bitmap, mem->pages, order); if (pageno < 0) return NULL; - *phys_addr = mem->phys_base + (pageno << page_shift); + *phys_addr = mem->window.phys_base + (pageno << page_shift); virt_addr = ioremap(*phys_addr, size); - if (!virt_addr) + if (!virt_addr) { bitmap_release_region(mem->bitmap, pageno, order); + } else { + mem->window.map_size += size; + *window = best_fit; + } return virt_addr; } EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); +static int pci_epc_get_matching_window(struct pci_epc *epc, + phys_addr_t phys_addr) +{ + struct pci_epc_mem *mem; + int i; + + for (i = 0; i < epc->mem_windows; i++) { + mem = epc->mem[i]; + + if (mem->window.phys_base == phys_addr) + return i; + } + + return -EINVAL; +} + /** * pci_epc_mem_free_addr() - free the allocated memory address * @epc: the EPC device on which memory was allocated @@ -155,16 +281,26 @@ EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr, void __iomem *virt_addr, size_t size) { + struct pci_epc_mem *mem; + unsigned int page_shift; + int window = 0; int pageno; - struct pci_epc_mem *mem = epc->mem; - unsigned int page_shift = ilog2(mem->page_size); int order; + if (epc->mem_windows > 1) { + window = pci_epc_get_matching_window(epc, phys_addr); + if (window < 0) + return; + } + + mem = epc->mem[window]; + page_shift = ilog2(mem->page_size); iounmap(virt_addr); - pageno = (phys_addr - mem->phys_base) >> page_shift; + pageno = (phys_addr - mem->window.phys_base) >> page_shift; size = ALIGN(size, mem->page_size); order = pci_epc_mem_get_order(mem, size); bitmap_release_region(mem->bitmap, pageno, order); + mem->window.map_size -= size; } EXPORT_SYMBOL_GPL(pci_epc_mem_free_addr); diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index f641bad..bee6f65 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -48,7 +48,8 @@ struct pci_epc_ops { void (*clear_bar)(struct pci_epc *epc, u8 func_no, struct pci_epf_bar *epf_bar); int (*map_addr)(struct pci_epc *epc, u8 func_no, - phys_addr_t addr, u64 pci_addr, size_t size); + phys_addr_t addr, int window, + u64 pci_addr, size_t size); void (*unmap_addr)(struct pci_epc *epc, u8 func_no, phys_addr_t addr); int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts); @@ -64,17 +65,57 @@ struct pci_epc_ops { struct module *owner; }; +#define PCI_EPC_DEFAULT_WINDOW 0 + +/** + * enum pci_epc_window_flags - flags info for pci_epc_mem_window + * + * This enum defines how the endpoint controller window should be used + * for allocations. + * + * @PCI_EPC_WINDOW_FLAG_MULTI_ALLOC: Indicates multiple chunks of memory can be + * allocated from same window + * @PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC: Indicates only single memory allocation + * is possible on the window + * @PCI_EPC_WINDOW_FLAG_LARGE_ALLOC: Window is used for large memory allocation + * @PCI_EPC_WINDOW_FLAG_SMALL_ALLOC: Window is used for small memory allocation + * @PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC: Window is used for high priority data + * transfers + * @PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC: Window is used for low priority data + * transfers + */ +enum pci_epc_window_flags { + PCI_EPC_WINDOW_FLAG_MULTI_ALLOC = BIT(0), + PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC = BIT(1), + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC = BIT(2), + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC = BIT(3), + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC = BIT(4), + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC = BIT(5), +}; + +/** + * struct pci_epc_mem_window - address window of the endpoint controller + * @phys_base: physical base address of the PCI address window + * @size: the size of the PCI address window + * @map_size: size of allocated chunk in window + * @flags: flags indicating how window can be used + */ +struct pci_epc_mem_window { + phys_addr_t phys_base; + size_t size; + size_t map_size; + u32 flags; +}; + /** * struct pci_epc_mem - address space of the endpoint controller - * @phys_base: physical base address of the PCI address space - * @size: the size of the PCI address space + * @window: address window of the endpoint controller * @bitmap: bitmap to manage the PCI address space - * @pages: number of bits representing the address region * @page_size: size of each page + * @pages: number of bits representing the address region */ struct pci_epc_mem { - phys_addr_t phys_base; - size_t size; + struct pci_epc_mem_window window; unsigned long *bitmap; size_t page_size; int pages; @@ -85,7 +126,8 @@ struct pci_epc_mem { * @dev: PCI EPC device * @pci_epf: list of endpoint functions present in this EPC device * @ops: function pointers for performing endpoint operations - * @mem: address space of the endpoint controller + * @mem: array of address space of the endpoint controller + * @mem_windows: number of windows supported by device * @max_functions: max number of functions that can be configured in this EPC * @group: configfs group representing the PCI EPC device * @lock: spinlock to protect pci_epc ops @@ -94,7 +136,8 @@ struct pci_epc { struct device dev; struct list_head pci_epf; const struct pci_epc_ops *ops; - struct pci_epc_mem *mem; + struct pci_epc_mem **mem; + int mem_windows; u8 max_functions; struct config_group *group; /* spinlock to protect against concurrent access of EP controller */ @@ -128,8 +171,8 @@ struct pci_epc_features { #define devm_pci_epc_create(dev, ops) \ __devm_pci_epc_create((dev), (ops), THIS_MODULE) -#define pci_epc_mem_init(epc, phys_addr, size) \ - __pci_epc_mem_init((epc), (phys_addr), (size), PAGE_SIZE) +#define pci_epc_mem_init(epc, windows, num_windows) \ + __pci_epc_mem_init((epc), windows, num_windows, PAGE_SIZE) static inline void epc_set_drvdata(struct pci_epc *epc, void *data) { @@ -159,7 +202,7 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, struct pci_epf_bar *epf_bar); int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, - phys_addr_t phys_addr, + phys_addr_t phys_addr, int window, u64 pci_addr, size_t size); void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, phys_addr_t phys_addr); @@ -178,11 +221,12 @@ unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features struct pci_epc *pci_epc_get(const char *epc_name); void pci_epc_put(struct pci_epc *epc); -int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_addr, size_t size, - size_t page_size); +int __pci_epc_mem_init(struct pci_epc *epc, struct pci_epc_mem_window *window, + int num_windows, size_t page_size); void pci_epc_mem_exit(struct pci_epc *epc); void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, - phys_addr_t *phys_addr, size_t size); + phys_addr_t *phys_addr, + int *window, size_t size, uint32_t flags); void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr, void __iomem *virt_addr, size_t size); #endif /* __LINUX_PCI_EPC_H */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [v2 2/6] pci: endpoint: add support to handle features of outbound memory 2019-12-13 8:47 ` [v2 2/6] pci: endpoint: add support to handle features of outbound memory Lad Prabhakar @ 2019-12-13 21:06 ` Bjorn Helgaas 2019-12-16 8:21 ` Lad, Prabhakar 2019-12-16 11:35 ` Kishon Vijay Abraham I 1 sibling, 1 reply; 27+ messages in thread From: Bjorn Helgaas @ 2019-12-13 21:06 UTC (permalink / raw) To: Lad Prabhakar Cc: Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel, linux-arm-kernel, linux-renesas-soc, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar On Fri, Dec 13, 2019 at 08:47:44AM +0000, Lad Prabhakar wrote: > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > rcar pcie controller has support to map multiple memory regions > for mapping the outbound memory in local system, this feature > inspires to add support for handling such features in endpoint > framework. similar features exists on other controllers where > outbound regions can be specifically used for low/high priority > transactions, and regions can be flagged and used for allocation > of large/small memory allocations. > This patch adds support to handle such features, where the > properties described for outbound regions are used whenever a > request to memory is made. For this and the other patches, please: - start sentences with a capital letter - leave a blank line between paragraphs - wrap commit log text to use the whole 80 character line (I wrap to 75 characters to account for "git log" indenting by 4 spaces) - check your signed-off-by: it shows your name as "Lad, Prabhakar", while your email From: line shows "Lad Prabhakar". Choose one :) > diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c > index 2bf8bd1..4b610cd 100644 > --- a/drivers/pci/endpoint/pci-epc-mem.c > +++ b/drivers/pci/endpoint/pci-epc-mem.c > -int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_base, size_t size, > - size_t page_size) > +int __pci_epc_mem_init(struct pci_epc *epc, struct pci_epc_mem_window *windows, > + int num_windows, size_t page_size) > { > - int ret; > - struct pci_epc_mem *mem; > - unsigned long *bitmap; > + struct pci_epc_mem *mem = NULL; > + unsigned long *bitmap = NULL; > unsigned int page_shift; > - int pages; > int bitmap_size; > + int pages; > + int ret; > + int i; > + > + epc->mem_windows = 0; > + > + if (!windows) > + return -EINVAL; > + > + if (num_windows <= 0) > + return -EINVAL; Why is num_windows signed? > void pci_epc_mem_exit(struct pci_epc *epc) > { > - struct pci_epc_mem *mem = epc->mem; > + struct pci_epc_mem *mem; > + int i; > + > + if (!epc->mem_windows) > + return; If you fix the loop below, why do you even need to test this? > + for (i = 0; i <= epc->mem_windows; i--) { Huh? "<="? "i--"? Surely you mean for (i = 0; i < epc->mem_windows; i++) { > + mem = epc->mem[i]; > + kfree(mem->bitmap); > + kfree(epc->mem[i]); > + } > + kfree(epc->mem); > > epc->mem = NULL; > - kfree(mem->bitmap); > - kfree(mem); > + epc->mem_windows = 0; > } > EXPORT_SYMBOL_GPL(pci_epc_mem_exit); > > +static int pci_epc_find_best_fit_window(struct pci_epc *epc, size_t size, > + u32 flags) Can this just return a struct pci_epc_mem *, so the caller doesn't have to lookup epc->mem[i] again? > +{ > + size_t window_least_size = 0; > + int best_fit_window = -1; > + struct pci_epc_mem *mem; > + size_t actual_size; > + size_t avail_size; > + u32 win_flags; > + int i; > + > + for (i = 0; i < epc->mem_windows; i++) { > + mem = epc->mem[i]; > + win_flags = mem->window.flags; > + > + actual_size = ALIGN(size, mem->page_size); > + avail_size = mem->window.size - mem->window.map_size; > + > + if (win_flags == 0x0) { > + if (best_fit_window == -1) { > + if (actual_size <= avail_size) { > + best_fit_window = i; > + window_least_size = mem->window.size; > + } > + } else { > + if (actual_size <= avail_size && > + mem->window.size < window_least_size) { > + best_fit_window = i; > + window_least_size = mem->window.size; > + } > + } > + } else { > + if (mem->window.map_size && > + (win_flags | PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC)) > + continue; > + > + if (!(win_flags | flags)) > + continue; > + > + if (best_fit_window == -1) { > + if (actual_size <= avail_size) { > + best_fit_window = i; > + window_least_size = mem->window.size; > + } > + } else { > + if (actual_size <= avail_size && > + mem->window.size < window_least_size) { > + best_fit_window = i; > + window_least_size = mem->window.size; > + } > + } > + } > + } > + > + return best_fit_window; > +} > + > /** > * pci_epc_mem_alloc_addr() - allocate memory address from EPC addr space > * @epc: the EPC device on which memory has to be allocated > * @phys_addr: populate the allocated physical address here > + * @window: populate the window here which will be used to map PCI address > * @size: the size of the address space that has to be allocated > + * @flags: look for window as requested in flags > * > * Invoke to allocate memory address from the EPC address space. This > * is usually done to map the remote RC address into the local system. > */ > void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, > - phys_addr_t *phys_addr, size_t size) > + phys_addr_t *phys_addr, > + int *window, size_t size, uint32_t flags) > { > + int best_fit = PCI_EPC_DEFAULT_WINDOW; > + void __iomem *virt_addr = NULL; > + struct pci_epc_mem *mem; > + unsigned int page_shift; > int pageno; > - void __iomem *virt_addr; > - struct pci_epc_mem *mem = epc->mem; > - unsigned int page_shift = ilog2(mem->page_size); > int order; > > + if (epc->mem_windows <= 0) > + return NULL; > + > + if (epc->mem_windows > 1) { Why bother testing epc->mem_windows here? Just make sure pci_epc_find_best_fit_window() returns the correct thing for "mem_windows == 0" and "mem_windows == 1", and remove both the tests above. > + best_fit = pci_epc_find_best_fit_window(epc, size, flags); > + if (best_fit < 0) > + return NULL; > + } > + > + mem = epc->mem[best_fit]; > size = ALIGN(size, mem->page_size); > + if (size > (mem->window.size - mem->window.map_size)) > + return NULL; > + page_shift = ilog2(mem->page_size); > order = pci_epc_mem_get_order(mem, size); > > pageno = bitmap_find_free_region(mem->bitmap, mem->pages, order); > if (pageno < 0) > return NULL; > > - *phys_addr = mem->phys_base + (pageno << page_shift); > + *phys_addr = mem->window.phys_base + (pageno << page_shift); > virt_addr = ioremap(*phys_addr, size); > - if (!virt_addr) > + if (!virt_addr) { > bitmap_release_region(mem->bitmap, pageno, order); > + } else { > + mem->window.map_size += size; > + *window = best_fit; > + } > > return virt_addr; > } > EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); > > +static int pci_epc_get_matching_window(struct pci_epc *epc, > + phys_addr_t phys_addr) Return struct pci_epc_mem * again? > +{ > + struct pci_epc_mem *mem; > + int i; > + > + for (i = 0; i < epc->mem_windows; i++) { > + mem = epc->mem[i]; > + > + if (mem->window.phys_base == phys_addr) > + return i; > + } > + > + return -EINVAL; > +} > + > /** > * pci_epc_mem_free_addr() - free the allocated memory address > * @epc: the EPC device on which memory was allocated > @@ -155,16 +281,26 @@ EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); > void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr, > void __iomem *virt_addr, size_t size) > { > + struct pci_epc_mem *mem; > + unsigned int page_shift; > + int window = 0; > int pageno; > - struct pci_epc_mem *mem = epc->mem; > - unsigned int page_shift = ilog2(mem->page_size); > int order; > > + if (epc->mem_windows > 1) { Same here (unnecessary test). > + window = pci_epc_get_matching_window(epc, phys_addr); > + if (window < 0) > + return; > + } > + > + mem = epc->mem[window]; > + page_shift = ilog2(mem->page_size); > iounmap(virt_addr); > - pageno = (phys_addr - mem->phys_base) >> page_shift; > + pageno = (phys_addr - mem->window.phys_base) >> page_shift; > size = ALIGN(size, mem->page_size); > order = pci_epc_mem_get_order(mem, size); > bitmap_release_region(mem->bitmap, pageno, order); > + mem->window.map_size -= size; > } > EXPORT_SYMBOL_GPL(pci_epc_mem_free_addr); > @@ -85,7 +126,8 @@ struct pci_epc_mem { > * @dev: PCI EPC device > * @pci_epf: list of endpoint functions present in this EPC device > * @ops: function pointers for performing endpoint operations > - * @mem: address space of the endpoint controller > + * @mem: array of address space of the endpoint controller > + * @mem_windows: number of windows supported by device > * @max_functions: max number of functions that can be configured in this EPC > * @group: configfs group representing the PCI EPC device > * @lock: spinlock to protect pci_epc ops > @@ -94,7 +136,8 @@ struct pci_epc { > struct device dev; > struct list_head pci_epf; > const struct pci_epc_ops *ops; > - struct pci_epc_mem *mem; > + struct pci_epc_mem **mem; > + int mem_windows; Can't this be unsigned int and then there's no need to check "mem_windows < 0"? > u8 max_functions; > struct config_group *group; > /* spinlock to protect against concurrent access of EP controller */ ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 2/6] pci: endpoint: add support to handle features of outbound memory 2019-12-13 21:06 ` Bjorn Helgaas @ 2019-12-16 8:21 ` Lad, Prabhakar 0 siblings, 0 replies; 27+ messages in thread From: Lad, Prabhakar @ 2019-12-16 8:21 UTC (permalink / raw) To: Bjorn Helgaas Cc: Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML, LAK, Linux-Renesas, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar Hi Bjorn, thank you for the review. On Fri, Dec 13, 2019 at 9:06 PM Bjorn Helgaas <helgaas@kernel.org> wrote: > > On Fri, Dec 13, 2019 at 08:47:44AM +0000, Lad Prabhakar wrote: > > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > rcar pcie controller has support to map multiple memory regions > > for mapping the outbound memory in local system, this feature > > inspires to add support for handling such features in endpoint > > framework. similar features exists on other controllers where > > outbound regions can be specifically used for low/high priority > > transactions, and regions can be flagged and used for allocation > > of large/small memory allocations. > > This patch adds support to handle such features, where the > > properties described for outbound regions are used whenever a > > request to memory is made. > > For this and the other patches, please: > > - start sentences with a capital letter > - leave a blank line between paragraphs > - wrap commit log text to use the whole 80 character line (I wrap to > 75 characters to account for "git log" indenting by 4 spaces) > - check your signed-off-by: it shows your name as "Lad, Prabhakar", > while your email From: line shows "Lad Prabhakar". Choose one :) > sure will fix it next version. > > diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c > > index 2bf8bd1..4b610cd 100644 > > --- a/drivers/pci/endpoint/pci-epc-mem.c > > +++ b/drivers/pci/endpoint/pci-epc-mem.c > > > -int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_base, size_t size, > > - size_t page_size) > > +int __pci_epc_mem_init(struct pci_epc *epc, struct pci_epc_mem_window *windows, > > + int num_windows, size_t page_size) > > { > > - int ret; > > - struct pci_epc_mem *mem; > > - unsigned long *bitmap; > > + struct pci_epc_mem *mem = NULL; > > + unsigned long *bitmap = NULL; > > unsigned int page_shift; > > - int pages; > > int bitmap_size; > > + int pages; > > + int ret; > > + int i; > > + > > + epc->mem_windows = 0; > > + > > + if (!windows) > > + return -EINVAL; > > + > > + if (num_windows <= 0) > > + return -EINVAL; > > Why is num_windows signed? > > > void pci_epc_mem_exit(struct pci_epc *epc) > > { > > - struct pci_epc_mem *mem = epc->mem; > > + struct pci_epc_mem *mem; > > + int i; > > + > > + if (!epc->mem_windows) > > + return; > > If you fix the loop below, why do you even need to test this? > yes makes sense will drop this check. > > + for (i = 0; i <= epc->mem_windows; i--) { > > Huh? "<="? "i--"? Surely you mean > > for (i = 0; i < epc->mem_windows; i++) { > oops my bad, will fix it. > > + mem = epc->mem[i]; > > + kfree(mem->bitmap); > > + kfree(epc->mem[i]); > > + } > > + kfree(epc->mem); > > > > epc->mem = NULL; > > - kfree(mem->bitmap); > > - kfree(mem); > > + epc->mem_windows = 0; > > } > > EXPORT_SYMBOL_GPL(pci_epc_mem_exit); > > > > +static int pci_epc_find_best_fit_window(struct pci_epc *epc, size_t size, > > + u32 flags) > > Can this just return a struct pci_epc_mem *, so the caller doesn't > have to lookup epc->mem[i] again? > yes makes sense will change it to return struct pci_epc_mem * > > +{ > > + size_t window_least_size = 0; > > + int best_fit_window = -1; > > + struct pci_epc_mem *mem; > > + size_t actual_size; > > + size_t avail_size; > > + u32 win_flags; > > + int i; > > + > > + for (i = 0; i < epc->mem_windows; i++) { > > + mem = epc->mem[i]; > > + win_flags = mem->window.flags; > > + > > + actual_size = ALIGN(size, mem->page_size); > > + avail_size = mem->window.size - mem->window.map_size; > > + > > + if (win_flags == 0x0) { > > + if (best_fit_window == -1) { > > + if (actual_size <= avail_size) { > > + best_fit_window = i; > > + window_least_size = mem->window.size; > > + } > > + } else { > > + if (actual_size <= avail_size && > > + mem->window.size < window_least_size) { > > + best_fit_window = i; > > + window_least_size = mem->window.size; > > + } > > + } > > + } else { > > + if (mem->window.map_size && > > + (win_flags | PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC)) > > + continue; > > + > > + if (!(win_flags | flags)) > > + continue; > > + > > + if (best_fit_window == -1) { > > + if (actual_size <= avail_size) { > > + best_fit_window = i; > > + window_least_size = mem->window.size; > > + } > > + } else { > > + if (actual_size <= avail_size && > > + mem->window.size < window_least_size) { > > + best_fit_window = i; > > + window_least_size = mem->window.size; > > + } > > + } > > + } > > + } > > + > > + return best_fit_window; > > +} > > + > > /** > > * pci_epc_mem_alloc_addr() - allocate memory address from EPC addr space > > * @epc: the EPC device on which memory has to be allocated > > * @phys_addr: populate the allocated physical address here > > + * @window: populate the window here which will be used to map PCI address > > * @size: the size of the address space that has to be allocated > > + * @flags: look for window as requested in flags > > * > > * Invoke to allocate memory address from the EPC address space. This > > * is usually done to map the remote RC address into the local system. > > */ > > void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, > > - phys_addr_t *phys_addr, size_t size) > > + phys_addr_t *phys_addr, > > + int *window, size_t size, uint32_t flags) > > { > > + int best_fit = PCI_EPC_DEFAULT_WINDOW; > > + void __iomem *virt_addr = NULL; > > + struct pci_epc_mem *mem; > > + unsigned int page_shift; > > int pageno; > > - void __iomem *virt_addr; > > - struct pci_epc_mem *mem = epc->mem; > > - unsigned int page_shift = ilog2(mem->page_size); > > int order; > > > > + if (epc->mem_windows <= 0) > > + return NULL; > > + > > + if (epc->mem_windows > 1) { > > Why bother testing epc->mem_windows here? Just make sure > pci_epc_find_best_fit_window() returns the correct thing for > "mem_windows == 0" and "mem_windows == 1", and remove both the tests > above. > will fix that. > > + best_fit = pci_epc_find_best_fit_window(epc, size, flags); > > + if (best_fit < 0) > > + return NULL; > > + } > > + > > + mem = epc->mem[best_fit]; > > size = ALIGN(size, mem->page_size); > > + if (size > (mem->window.size - mem->window.map_size)) > > + return NULL; > > + page_shift = ilog2(mem->page_size); > > order = pci_epc_mem_get_order(mem, size); > > > > pageno = bitmap_find_free_region(mem->bitmap, mem->pages, order); > > if (pageno < 0) > > return NULL; > > > > - *phys_addr = mem->phys_base + (pageno << page_shift); > > + *phys_addr = mem->window.phys_base + (pageno << page_shift); > > virt_addr = ioremap(*phys_addr, size); > > - if (!virt_addr) > > + if (!virt_addr) { > > bitmap_release_region(mem->bitmap, pageno, order); > > + } else { > > + mem->window.map_size += size; > > + *window = best_fit; > > + } > > > > return virt_addr; > > } > > EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); > > > > +static int pci_epc_get_matching_window(struct pci_epc *epc, > > + phys_addr_t phys_addr) > > Return struct pci_epc_mem * again? > yes makes sense. > > +{ > > + struct pci_epc_mem *mem; > > + int i; > > + > > + for (i = 0; i < epc->mem_windows; i++) { > > + mem = epc->mem[i]; > > + > > + if (mem->window.phys_base == phys_addr) > > + return i; > > + } > > + > > + return -EINVAL; > > +} > > + > > /** > > * pci_epc_mem_free_addr() - free the allocated memory address > > * @epc: the EPC device on which memory was allocated > > @@ -155,16 +281,26 @@ EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); > > void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr, > > void __iomem *virt_addr, size_t size) > > { > > + struct pci_epc_mem *mem; > > + unsigned int page_shift; > > + int window = 0; > > int pageno; > > - struct pci_epc_mem *mem = epc->mem; > > - unsigned int page_shift = ilog2(mem->page_size); > > int order; > > > > + if (epc->mem_windows > 1) { > > Same here (unnecessary test). > will drop it. > > + window = pci_epc_get_matching_window(epc, phys_addr); > > + if (window < 0) > > + return; > > + } > > + > > + mem = epc->mem[window]; > > + page_shift = ilog2(mem->page_size); > > iounmap(virt_addr); > > - pageno = (phys_addr - mem->phys_base) >> page_shift; > > + pageno = (phys_addr - mem->window.phys_base) >> page_shift; > > size = ALIGN(size, mem->page_size); > > order = pci_epc_mem_get_order(mem, size); > > bitmap_release_region(mem->bitmap, pageno, order); > > + mem->window.map_size -= size; > > } > > EXPORT_SYMBOL_GPL(pci_epc_mem_free_addr); > > > @@ -85,7 +126,8 @@ struct pci_epc_mem { > > * @dev: PCI EPC device > > * @pci_epf: list of endpoint functions present in this EPC device > > * @ops: function pointers for performing endpoint operations > > - * @mem: address space of the endpoint controller > > + * @mem: array of address space of the endpoint controller > > + * @mem_windows: number of windows supported by device > > * @max_functions: max number of functions that can be configured in this EPC > > * @group: configfs group representing the PCI EPC device > > * @lock: spinlock to protect pci_epc ops > > @@ -94,7 +136,8 @@ struct pci_epc { > > struct device dev; > > struct list_head pci_epf; > > const struct pci_epc_ops *ops; > > - struct pci_epc_mem *mem; > > + struct pci_epc_mem **mem; > > + int mem_windows; > > Can't this be unsigned int and then there's no need to check > "mem_windows < 0"? > yes will change it unsigned int. Cheers, --Prabhakar > > u8 max_functions; > > struct config_group *group; > > /* spinlock to protect against concurrent access of EP controller */ ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 2/6] pci: endpoint: add support to handle features of outbound memory 2019-12-13 8:47 ` [v2 2/6] pci: endpoint: add support to handle features of outbound memory Lad Prabhakar 2019-12-13 21:06 ` Bjorn Helgaas @ 2019-12-16 11:35 ` Kishon Vijay Abraham I 2019-12-18 17:23 ` Lad, Prabhakar 1 sibling, 1 reply; 27+ messages in thread From: Kishon Vijay Abraham I @ 2019-12-16 11:35 UTC (permalink / raw) To: Lad Prabhakar, Bjorn Helgaas, Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Marek Vasut, Yoshihiro Shimoda, linux-pci Cc: Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel, linux-arm-kernel, linux-renesas-soc, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar Hi Prabhakar, On 13/12/19 2:17 pm, wrote: > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > rcar pcie controller has support to map multiple memory regions > for mapping the outbound memory in local system, this feature > inspires to add support for handling such features in endpoint > framework. similar features exists on other controllers where > outbound regions can be specifically used for low/high priority > transactions, and regions can be flagged and used for allocation > of large/small memory allocations. > This patch adds support to handle such features, where the > properties described for outbound regions are used whenever a > request to memory is made. > > Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > drivers/pci/controller/dwc/pcie-designware-ep.c | 30 ++-- > drivers/pci/controller/pcie-cadence-ep.c | 11 +- > drivers/pci/controller/pcie-rockchip-ep.c | 13 +- > drivers/pci/endpoint/functions/pci-epf-test.c | 47 ++++-- > drivers/pci/endpoint/pci-epc-core.c | 7 +- > drivers/pci/endpoint/pci-epc-mem.c | 216 +++++++++++++++++++----- > include/linux/pci-epc.h | 72 ++++++-- > 7 files changed, 307 insertions(+), 89 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index 3dd2e26..be6aa94 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -195,7 +195,7 @@ static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no, > } > > static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, > - phys_addr_t addr, > + phys_addr_t addr, int window, > u64 pci_addr, size_t size) > { > int ret; > @@ -367,6 +367,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, > unsigned int aligned_offset; > u16 msg_ctrl, msg_data; > u32 msg_addr_lower, msg_addr_upper, reg; > + int window = PCI_EPC_DEFAULT_WINDOW; > u64 msg_addr; > bool has_upper; > int ret; > @@ -390,11 +391,11 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, > reg = ep->msi_cap + PCI_MSI_DATA_32; > msg_data = dw_pcie_readw_dbi(pci, reg); > } > - aligned_offset = msg_addr_lower & (epc->mem->page_size - 1); > + aligned_offset = msg_addr_lower & (epc->mem[window]->page_size - 1); > msg_addr = ((u64)msg_addr_upper) << 32 | > (msg_addr_lower & ~aligned_offset); > - ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, > - epc->mem->page_size); > + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, window, > + msg_addr, epc->mem[window]->page_size); > if (ret) > return ret; > > @@ -416,6 +417,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > u32 reg, msg_data, vec_ctrl; > u64 tbl_addr, msg_addr, reg_u64; > void __iomem *msix_tbl; > + int window = PCI_EPC_DEFAULT_WINDOW; > int ret; > > reg = ep->msix_cap + PCI_MSIX_TABLE; > @@ -452,8 +454,8 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > return -EPERM; > } > > - ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, > - epc->mem->page_size); > + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, window, > + msg_addr, epc->mem[window]->page_size); > if (ret) > return ret; > > @@ -466,10 +468,11 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > > void dw_pcie_ep_exit(struct dw_pcie_ep *ep) > { > + int window = PCI_EPC_DEFAULT_WINDOW; > struct pci_epc *epc = ep->epc; > > pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, > - epc->mem->page_size); > + epc->mem[window]->page_size); > > pci_epc_mem_exit(epc); > } > @@ -499,9 +502,12 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > u32 reg; > void *addr; > u8 hdr_type; > + int window; > unsigned int nbars; > unsigned int offset; > struct pci_epc *epc; > + size_t msi_page_size; > + struct pci_epc_mem_window mem_window; > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > struct device *dev = pci->dev; > struct device_node *np = dev->of_node; > @@ -574,15 +580,17 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > if (ret < 0) > epc->max_functions = 1; > > - ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, > - ep->page_size); > + mem_window.phys_base = ep->phys_base; > + mem_window.size = ep->addr_size; > + ret = __pci_epc_mem_init(epc, &mem_window, 1, ep->page_size); > if (ret < 0) { > dev_err(dev, "Failed to initialize address space\n"); > return ret; > } > > - ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, > - epc->mem->page_size); > + msi_page_size = epc->mem[PCI_EPC_DEFAULT_WINDOW]->page_size; > + ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, &window, > + msi_page_size, 0x0); > if (!ep->msi_mem) { > dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); > return -ENOMEM; > diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c > index def7820..2410706 100644 > --- a/drivers/pci/controller/pcie-cadence-ep.c > +++ b/drivers/pci/controller/pcie-cadence-ep.c > @@ -172,7 +172,7 @@ static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, > } > > static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr, > - u64 pci_addr, size_t size) > + int window, u64 pci_addr, size_t size) > { > struct cdns_pcie_ep *ep = epc_get_drvdata(epc); > struct cdns_pcie *pcie = &ep->pcie; > @@ -434,12 +434,14 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct device_node *np = dev->of_node; > + struct pci_epc_mem_window mem_window; > struct cdns_pcie_ep *ep; > struct cdns_pcie *pcie; > struct pci_epc *epc; > struct resource *res; > int ret; > int phy_count; > + int window; > > ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); > if (!ep) > @@ -502,15 +504,16 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) > if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) > epc->max_functions = 1; > > - ret = pci_epc_mem_init(epc, pcie->mem_res->start, > - resource_size(pcie->mem_res)); > + mem_window.phys_base = pcie->mem_res->start; > + mem_window.size = resource_size(pcie->mem_res); > + ret = pci_epc_mem_init(epc, &mem_window, 1); > if (ret < 0) { > dev_err(dev, "failed to initialize the memory space\n"); > goto err_init; > } > > ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, > - SZ_128K); > + &window, SZ_128K, 0x0); > if (!ep->irq_cpu_addr) { > dev_err(dev, "failed to reserve memory space for MSI\n"); > ret = -ENOMEM; > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c > index d743b0a..828052c 100644 > --- a/drivers/pci/controller/pcie-rockchip-ep.c > +++ b/drivers/pci/controller/pcie-rockchip-ep.c > @@ -256,8 +256,8 @@ static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, > } > > static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, > - phys_addr_t addr, u64 pci_addr, > - size_t size) > + phys_addr_t addr, int window, > + u64 pci_addr, size_t size) > { > struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > struct rockchip_pcie *pcie = &ep->rockchip; > @@ -562,11 +562,13 @@ static const struct of_device_id rockchip_pcie_ep_of_match[] = { > > static int rockchip_pcie_ep_probe(struct platform_device *pdev) > { > + struct pci_epc_mem_window mem_window; > struct device *dev = &pdev->dev; > struct rockchip_pcie_ep *ep; > struct rockchip_pcie *rockchip; > struct pci_epc *epc; > size_t max_regions; > + int window; > int err; > > ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); > @@ -614,15 +616,16 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) > /* Only enable function 0 by default */ > rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); > > - err = pci_epc_mem_init(epc, rockchip->mem_res->start, > - resource_size(rockchip->mem_res)); > + mem_window.phys_base = rockchip->mem_res->start; > + mem_window.size = resource_size(rockchip->mem_res); > + err = pci_epc_mem_init(epc, &mem_window, 1); > if (err < 0) { > dev_err(dev, "failed to initialize the memory space\n"); > goto err_uninit_port; > } > > ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, > - SZ_128K); > + &window, SZ_128K, 0x0); > if (!ep->irq_cpu_addr) { > dev_err(dev, "failed to reserve memory space for MSI\n"); > err = -ENOMEM; > diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c > index 1cfe368..4768d54 100644 > --- a/drivers/pci/endpoint/functions/pci-epf-test.c > +++ b/drivers/pci/endpoint/functions/pci-epf-test.c > @@ -84,8 +84,14 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) > struct pci_epc *epc = epf->epc; > enum pci_barno test_reg_bar = epf_test->test_reg_bar; > struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; > - > - src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size); > + int window; > + > + src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, > + &window, reg->size, > + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | > + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | > + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | > + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); > if (!src_addr) { > dev_err(dev, "Failed to allocate source address\n"); > reg->status = STATUS_SRC_ADDR_INVALID; > @@ -93,15 +99,20 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) > goto err; > } > > - ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, reg->src_addr, > - reg->size); > + ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, window, > + reg->src_addr, reg->size); > if (ret) { > dev_err(dev, "Failed to map source address\n"); > reg->status = STATUS_SRC_ADDR_INVALID; > goto err_src_addr; > } > > - dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size); > + dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, > + &window, reg->size, > + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | > + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | > + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | > + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); > if (!dst_addr) { > dev_err(dev, "Failed to allocate destination address\n"); > reg->status = STATUS_DST_ADDR_INVALID; > @@ -109,8 +120,8 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) > goto err_src_map_addr; > } > > - ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, reg->dst_addr, > - reg->size); > + ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, window, > + reg->dst_addr, reg->size); > if (ret) { > dev_err(dev, "Failed to map destination address\n"); > reg->status = STATUS_DST_ADDR_INVALID; > @@ -146,8 +157,13 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test) > struct pci_epc *epc = epf->epc; > enum pci_barno test_reg_bar = epf_test->test_reg_bar; > struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; > + int window; > > - src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); > + src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, &window, reg->size, > + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | > + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | > + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | > + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); > if (!src_addr) { > dev_err(dev, "Failed to allocate address\n"); > reg->status = STATUS_SRC_ADDR_INVALID; > @@ -155,8 +171,8 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test) > goto err; > } > > - ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->src_addr, > - reg->size); > + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, window, > + reg->src_addr, reg->size); > if (ret) { > dev_err(dev, "Failed to map address\n"); > reg->status = STATUS_SRC_ADDR_INVALID; > @@ -193,13 +209,18 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test) > void __iomem *dst_addr; > void *buf; > phys_addr_t phys_addr; > + int window; > struct pci_epf *epf = epf_test->epf; > struct device *dev = &epf->dev; > struct pci_epc *epc = epf->epc; > enum pci_barno test_reg_bar = epf_test->test_reg_bar; > struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; > > - dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); > + dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, &window, reg->size, > + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | > + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | > + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | > + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); > if (!dst_addr) { > dev_err(dev, "Failed to allocate address\n"); > reg->status = STATUS_DST_ADDR_INVALID; > @@ -207,8 +228,8 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test) > goto err; > } > > - ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->dst_addr, > - reg->size); > + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, window, > + reg->dst_addr, reg->size); > if (ret) { > dev_err(dev, "Failed to map address\n"); > reg->status = STATUS_DST_ADDR_INVALID; > diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c > index 2091508..289c266 100644 > --- a/drivers/pci/endpoint/pci-epc-core.c > +++ b/drivers/pci/endpoint/pci-epc-core.c > @@ -358,13 +358,15 @@ EXPORT_SYMBOL_GPL(pci_epc_unmap_addr); > * @epc: the EPC device on which address is allocated > * @func_no: the endpoint function number in the EPC device > * @phys_addr: physical address of the local system > + * @window: index to the window region where PCI address will be mapped > * @pci_addr: PCI address to which the physical address should be mapped > * @size: the size of the allocation > * > * Invoke to map CPU address with PCI address. > */ > int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, > - phys_addr_t phys_addr, u64 pci_addr, size_t size) > + phys_addr_t phys_addr, int window, > + u64 pci_addr, size_t size) > { > int ret; > unsigned long flags; > @@ -376,7 +378,8 @@ int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, > return 0; > > spin_lock_irqsave(&epc->lock, flags); > - ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size); > + ret = epc->ops->map_addr(epc, func_no, phys_addr, > + window, pci_addr, size); > spin_unlock_irqrestore(&epc->lock, flags); > > return ret; > diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c > index 2bf8bd1..4b610cd 100644 > --- a/drivers/pci/endpoint/pci-epc-mem.c > +++ b/drivers/pci/endpoint/pci-epc-mem.c > @@ -39,56 +39,78 @@ static int pci_epc_mem_get_order(struct pci_epc_mem *mem, size_t size) > * __pci_epc_mem_init() - initialize the pci_epc_mem structure > * @epc: the EPC device that invoked pci_epc_mem_init > * @phys_base: the physical address of the base > - * @size: the size of the address space > + * @num_windows: number of windows device supports > * @page_size: size of each page > * > * Invoke to initialize the pci_epc_mem structure used by the > * endpoint functions to allocate mapped PCI address. > */ > -int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_base, size_t size, > - size_t page_size) > +int __pci_epc_mem_init(struct pci_epc *epc, struct pci_epc_mem_window *windows, > + int num_windows, size_t page_size) > { > - int ret; > - struct pci_epc_mem *mem; > - unsigned long *bitmap; > + struct pci_epc_mem *mem = NULL; > + unsigned long *bitmap = NULL; > unsigned int page_shift; > - int pages; > int bitmap_size; > + int pages; > + int ret; > + int i; > + > + epc->mem_windows = 0; > + > + if (!windows) > + return -EINVAL; > + > + if (num_windows <= 0) > + return -EINVAL; > > if (page_size < PAGE_SIZE) > page_size = PAGE_SIZE; > > page_shift = ilog2(page_size); > - pages = size >> page_shift; > - bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); > > - mem = kzalloc(sizeof(*mem), GFP_KERNEL); > - if (!mem) { > - ret = -ENOMEM; > - goto err; > - } > + epc->mem = kcalloc(num_windows, sizeof(*mem), GFP_KERNEL); > + if (!epc->mem) > + return -EINVAL; > > - bitmap = kzalloc(bitmap_size, GFP_KERNEL); > - if (!bitmap) { > - ret = -ENOMEM; > - goto err_mem; > - } > + for (i = 0; i < num_windows; i++) { > + pages = windows[i].phys_base >> page_shift; > + bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); > > - mem->bitmap = bitmap; > - mem->phys_base = phys_base; > - mem->page_size = page_size; > - mem->pages = pages; > - mem->size = size; > + mem = kzalloc(sizeof(*mem), GFP_KERNEL); > + if (!mem) { > + ret = -ENOMEM; > + goto err_mem; > + } > > - epc->mem = mem; > + bitmap = kzalloc(bitmap_size, GFP_KERNEL); > + if (!bitmap) { > + ret = -ENOMEM; > + goto err_mem; > + } > + > + mem->bitmap = bitmap; > + mem->window.phys_base = windows[i].phys_base; > + mem->page_size = page_size; > + mem->pages = pages; > + mem->window.size = windows[i].size; > + mem->window.map_size = 0; > + mem->window.flags = windows[i].flags; > + > + epc->mem[i] = mem; > + } > + epc->mem_windows = num_windows; > > return 0; > > err_mem: > - kfree(mem); > + for (; i >= 0; i--) { > + kfree(mem->bitmap); > + kfree(epc->mem[i]); > + } > + kfree(epc->mem); > > -err: > -return ret; > + return ret; > } > EXPORT_SYMBOL_GPL(__pci_epc_mem_init); > > @@ -101,48 +123,152 @@ EXPORT_SYMBOL_GPL(__pci_epc_mem_init); > */ > void pci_epc_mem_exit(struct pci_epc *epc) > { > - struct pci_epc_mem *mem = epc->mem; > + struct pci_epc_mem *mem; > + int i; > + > + if (!epc->mem_windows) > + return; > + > + for (i = 0; i <= epc->mem_windows; i--) { > + mem = epc->mem[i]; > + kfree(mem->bitmap); > + kfree(epc->mem[i]); > + } > + kfree(epc->mem); > > epc->mem = NULL; > - kfree(mem->bitmap); > - kfree(mem); > + epc->mem_windows = 0; > } > EXPORT_SYMBOL_GPL(pci_epc_mem_exit); > > +static int pci_epc_find_best_fit_window(struct pci_epc *epc, size_t size, > + u32 flags) > +{ > + size_t window_least_size = 0; > + int best_fit_window = -1; > + struct pci_epc_mem *mem; > + size_t actual_size; > + size_t avail_size; > + u32 win_flags; > + int i; > + > + for (i = 0; i < epc->mem_windows; i++) { > + mem = epc->mem[i]; > + win_flags = mem->window.flags; > + > + actual_size = ALIGN(size, mem->page_size); > + avail_size = mem->window.size - mem->window.map_size; > + > + if (win_flags == 0x0) { > + if (best_fit_window == -1) { > + if (actual_size <= avail_size) { > + best_fit_window = i; > + window_least_size = mem->window.size; > + } > + } else { > + if (actual_size <= avail_size && > + mem->window.size < window_least_size) { > + best_fit_window = i; > + window_least_size = mem->window.size; > + } > + } > + } else { > + if (mem->window.map_size && > + (win_flags | PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC)) > + continue; > + > + if (!(win_flags | flags)) > + continue; > + > + if (best_fit_window == -1) { > + if (actual_size <= avail_size) { > + best_fit_window = i; > + window_least_size = mem->window.size; > + } > + } else { > + if (actual_size <= avail_size && > + mem->window.size < window_least_size) { > + best_fit_window = i; > + window_least_size = mem->window.size; > + } > + } > + } > + } > + > + return best_fit_window; > +} > + > /** > * pci_epc_mem_alloc_addr() - allocate memory address from EPC addr space > * @epc: the EPC device on which memory has to be allocated > * @phys_addr: populate the allocated physical address here > + * @window: populate the window here which will be used to map PCI address > * @size: the size of the address space that has to be allocated > + * @flags: look for window as requested in flags > * > * Invoke to allocate memory address from the EPC address space. This > * is usually done to map the remote RC address into the local system. > */ > void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, > - phys_addr_t *phys_addr, size_t size) > + phys_addr_t *phys_addr, > + int *window, size_t size, uint32_t flags) > { > + int best_fit = PCI_EPC_DEFAULT_WINDOW; > + void __iomem *virt_addr = NULL; > + struct pci_epc_mem *mem; > + unsigned int page_shift; > int pageno; > - void __iomem *virt_addr; > - struct pci_epc_mem *mem = epc->mem; > - unsigned int page_shift = ilog2(mem->page_size); > int order; > > + if (epc->mem_windows <= 0) > + return NULL; > + > + if (epc->mem_windows > 1) { > + best_fit = pci_epc_find_best_fit_window(epc, size, flags); > + if (best_fit < 0) > + return NULL; > + } > + > + mem = epc->mem[best_fit]; > size = ALIGN(size, mem->page_size); > + if (size > (mem->window.size - mem->window.map_size)) > + return NULL; > + page_shift = ilog2(mem->page_size); > order = pci_epc_mem_get_order(mem, size); > > pageno = bitmap_find_free_region(mem->bitmap, mem->pages, order); > if (pageno < 0) > return NULL; > > - *phys_addr = mem->phys_base + (pageno << page_shift); > + *phys_addr = mem->window.phys_base + (pageno << page_shift); > virt_addr = ioremap(*phys_addr, size); > - if (!virt_addr) > + if (!virt_addr) { > bitmap_release_region(mem->bitmap, pageno, order); > + } else { > + mem->window.map_size += size; > + *window = best_fit; > + } > > return virt_addr; > } > EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); > > +static int pci_epc_get_matching_window(struct pci_epc *epc, > + phys_addr_t phys_addr) > +{ > + struct pci_epc_mem *mem; > + int i; > + > + for (i = 0; i < epc->mem_windows; i++) { > + mem = epc->mem[i]; > + > + if (mem->window.phys_base == phys_addr) > + return i; > + } > + > + return -EINVAL; > +} > + > /** > * pci_epc_mem_free_addr() - free the allocated memory address > * @epc: the EPC device on which memory was allocated > @@ -155,16 +281,26 @@ EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); > void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr, > void __iomem *virt_addr, size_t size) > { > + struct pci_epc_mem *mem; > + unsigned int page_shift; > + int window = 0; > int pageno; > - struct pci_epc_mem *mem = epc->mem; > - unsigned int page_shift = ilog2(mem->page_size); > int order; > > + if (epc->mem_windows > 1) { > + window = pci_epc_get_matching_window(epc, phys_addr); > + if (window < 0) > + return; > + } > + > + mem = epc->mem[window]; > + page_shift = ilog2(mem->page_size); > iounmap(virt_addr); > - pageno = (phys_addr - mem->phys_base) >> page_shift; > + pageno = (phys_addr - mem->window.phys_base) >> page_shift; > size = ALIGN(size, mem->page_size); > order = pci_epc_mem_get_order(mem, size); > bitmap_release_region(mem->bitmap, pageno, order); > + mem->window.map_size -= size; > } > EXPORT_SYMBOL_GPL(pci_epc_mem_free_addr); > > diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h > index f641bad..bee6f65 100644 > --- a/include/linux/pci-epc.h > +++ b/include/linux/pci-epc.h > @@ -48,7 +48,8 @@ struct pci_epc_ops { > void (*clear_bar)(struct pci_epc *epc, u8 func_no, > struct pci_epf_bar *epf_bar); > int (*map_addr)(struct pci_epc *epc, u8 func_no, > - phys_addr_t addr, u64 pci_addr, size_t size); > + phys_addr_t addr, int window, > + u64 pci_addr, size_t size); > void (*unmap_addr)(struct pci_epc *epc, u8 func_no, > phys_addr_t addr); > int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts); > @@ -64,17 +65,57 @@ struct pci_epc_ops { > struct module *owner; > }; > > +#define PCI_EPC_DEFAULT_WINDOW 0 > + > +/** > + * enum pci_epc_window_flags - flags info for pci_epc_mem_window > + * > + * This enum defines how the endpoint controller window should be used > + * for allocations. > + * > + * @PCI_EPC_WINDOW_FLAG_MULTI_ALLOC: Indicates multiple chunks of memory can be > + * allocated from same window > + * @PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC: Indicates only single memory allocation > + * is possible on the window Instead of NON_MULTI_ALLOC, we could simply have different page_size for different windows. For a platform that doesn't allow multiple alloc, page size will be equal to the window size. > + * @PCI_EPC_WINDOW_FLAG_LARGE_ALLOC: Window is used for large memory allocation > + * @PCI_EPC_WINDOW_FLAG_SMALL_ALLOC: Window is used for small memory allocation > + * @PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC: Window is used for high priority data > + * transfers > + * @PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC: Window is used for low priority data > + * transfers Let's defer adding these flags until a platform actually starts to use this. Thanks Kishon ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 2/6] pci: endpoint: add support to handle features of outbound memory 2019-12-16 11:35 ` Kishon Vijay Abraham I @ 2019-12-18 17:23 ` Lad, Prabhakar 2020-01-02 9:44 ` Kishon Vijay Abraham I 0 siblings, 1 reply; 27+ messages in thread From: Lad, Prabhakar @ 2019-12-18 17:23 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Bjorn Helgaas, Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Marek Vasut, Yoshihiro Shimoda, linux-pci, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML, LAK, Linux-Renesas, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, open list:ARM/Rockchip SoC..., Lad, Prabhakar Hi Kishon, On Mon, Dec 16, 2019 at 11:34 AM Kishon Vijay Abraham I <kishon@ti.com> wrote: > > Hi Prabhakar, > > On 13/12/19 2:17 pm, wrote: > > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > rcar pcie controller has support to map multiple memory regions > > for mapping the outbound memory in local system, this feature > > inspires to add support for handling such features in endpoint > > framework. similar features exists on other controllers where > > outbound regions can be specifically used for low/high priority > > transactions, and regions can be flagged and used for allocation > > of large/small memory allocations. > > This patch adds support to handle such features, where the > > properties described for outbound regions are used whenever a > > request to memory is made. > > > > Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > drivers/pci/controller/dwc/pcie-designware-ep.c | 30 ++-- > > drivers/pci/controller/pcie-cadence-ep.c | 11 +- > > drivers/pci/controller/pcie-rockchip-ep.c | 13 +- > > drivers/pci/endpoint/functions/pci-epf-test.c | 47 ++++-- > > drivers/pci/endpoint/pci-epc-core.c | 7 +- > > drivers/pci/endpoint/pci-epc-mem.c | 216 +++++++++++++++++++----- > > include/linux/pci-epc.h | 72 ++++++-- > > 7 files changed, 307 insertions(+), 89 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > > index 3dd2e26..be6aa94 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > > @@ -195,7 +195,7 @@ static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no, > > } > > > > static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, > > - phys_addr_t addr, > > + phys_addr_t addr, int window, > > u64 pci_addr, size_t size) > > { > > int ret; > > @@ -367,6 +367,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, > > unsigned int aligned_offset; > > u16 msg_ctrl, msg_data; > > u32 msg_addr_lower, msg_addr_upper, reg; > > + int window = PCI_EPC_DEFAULT_WINDOW; > > u64 msg_addr; > > bool has_upper; > > int ret; > > @@ -390,11 +391,11 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, > > reg = ep->msi_cap + PCI_MSI_DATA_32; > > msg_data = dw_pcie_readw_dbi(pci, reg); > > } > > - aligned_offset = msg_addr_lower & (epc->mem->page_size - 1); > > + aligned_offset = msg_addr_lower & (epc->mem[window]->page_size - 1); > > msg_addr = ((u64)msg_addr_upper) << 32 | > > (msg_addr_lower & ~aligned_offset); > > - ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, > > - epc->mem->page_size); > > + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, window, > > + msg_addr, epc->mem[window]->page_size); > > if (ret) > > return ret; > > > > @@ -416,6 +417,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > > u32 reg, msg_data, vec_ctrl; > > u64 tbl_addr, msg_addr, reg_u64; > > void __iomem *msix_tbl; > > + int window = PCI_EPC_DEFAULT_WINDOW; > > int ret; > > > > reg = ep->msix_cap + PCI_MSIX_TABLE; > > @@ -452,8 +454,8 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > > return -EPERM; > > } > > > > - ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, > > - epc->mem->page_size); > > + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, window, > > + msg_addr, epc->mem[window]->page_size); > > if (ret) > > return ret; > > > > @@ -466,10 +468,11 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > > > > void dw_pcie_ep_exit(struct dw_pcie_ep *ep) > > { > > + int window = PCI_EPC_DEFAULT_WINDOW; > > struct pci_epc *epc = ep->epc; > > > > pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, > > - epc->mem->page_size); > > + epc->mem[window]->page_size); > > > > pci_epc_mem_exit(epc); > > } > > @@ -499,9 +502,12 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > > u32 reg; > > void *addr; > > u8 hdr_type; > > + int window; > > unsigned int nbars; > > unsigned int offset; > > struct pci_epc *epc; > > + size_t msi_page_size; > > + struct pci_epc_mem_window mem_window; > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > > struct device *dev = pci->dev; > > struct device_node *np = dev->of_node; > > @@ -574,15 +580,17 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > > if (ret < 0) > > epc->max_functions = 1; > > > > - ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, > > - ep->page_size); > > + mem_window.phys_base = ep->phys_base; > > + mem_window.size = ep->addr_size; > > + ret = __pci_epc_mem_init(epc, &mem_window, 1, ep->page_size); > > if (ret < 0) { > > dev_err(dev, "Failed to initialize address space\n"); > > return ret; > > } > > > > - ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, > > - epc->mem->page_size); > > + msi_page_size = epc->mem[PCI_EPC_DEFAULT_WINDOW]->page_size; > > + ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, &window, > > + msi_page_size, 0x0); > > if (!ep->msi_mem) { > > dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); > > return -ENOMEM; > > diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c > > index def7820..2410706 100644 > > --- a/drivers/pci/controller/pcie-cadence-ep.c > > +++ b/drivers/pci/controller/pcie-cadence-ep.c > > @@ -172,7 +172,7 @@ static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, > > } > > > > static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr, > > - u64 pci_addr, size_t size) > > + int window, u64 pci_addr, size_t size) > > { > > struct cdns_pcie_ep *ep = epc_get_drvdata(epc); > > struct cdns_pcie *pcie = &ep->pcie; > > @@ -434,12 +434,14 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) > > { > > struct device *dev = &pdev->dev; > > struct device_node *np = dev->of_node; > > + struct pci_epc_mem_window mem_window; > > struct cdns_pcie_ep *ep; > > struct cdns_pcie *pcie; > > struct pci_epc *epc; > > struct resource *res; > > int ret; > > int phy_count; > > + int window; > > > > ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); > > if (!ep) > > @@ -502,15 +504,16 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) > > if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) > > epc->max_functions = 1; > > > > - ret = pci_epc_mem_init(epc, pcie->mem_res->start, > > - resource_size(pcie->mem_res)); > > + mem_window.phys_base = pcie->mem_res->start; > > + mem_window.size = resource_size(pcie->mem_res); > > + ret = pci_epc_mem_init(epc, &mem_window, 1); > > if (ret < 0) { > > dev_err(dev, "failed to initialize the memory space\n"); > > goto err_init; > > } > > > > ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, > > - SZ_128K); > > + &window, SZ_128K, 0x0); > > if (!ep->irq_cpu_addr) { > > dev_err(dev, "failed to reserve memory space for MSI\n"); > > ret = -ENOMEM; > > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c > > index d743b0a..828052c 100644 > > --- a/drivers/pci/controller/pcie-rockchip-ep.c > > +++ b/drivers/pci/controller/pcie-rockchip-ep.c > > @@ -256,8 +256,8 @@ static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, > > } > > > > static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, > > - phys_addr_t addr, u64 pci_addr, > > - size_t size) > > + phys_addr_t addr, int window, > > + u64 pci_addr, size_t size) > > { > > struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > > struct rockchip_pcie *pcie = &ep->rockchip; > > @@ -562,11 +562,13 @@ static const struct of_device_id rockchip_pcie_ep_of_match[] = { > > > > static int rockchip_pcie_ep_probe(struct platform_device *pdev) > > { > > + struct pci_epc_mem_window mem_window; > > struct device *dev = &pdev->dev; > > struct rockchip_pcie_ep *ep; > > struct rockchip_pcie *rockchip; > > struct pci_epc *epc; > > size_t max_regions; > > + int window; > > int err; > > > > ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); > > @@ -614,15 +616,16 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) > > /* Only enable function 0 by default */ > > rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); > > > > - err = pci_epc_mem_init(epc, rockchip->mem_res->start, > > - resource_size(rockchip->mem_res)); > > + mem_window.phys_base = rockchip->mem_res->start; > > + mem_window.size = resource_size(rockchip->mem_res); > > + err = pci_epc_mem_init(epc, &mem_window, 1); > > if (err < 0) { > > dev_err(dev, "failed to initialize the memory space\n"); > > goto err_uninit_port; > > } > > > > ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, > > - SZ_128K); > > + &window, SZ_128K, 0x0); > > if (!ep->irq_cpu_addr) { > > dev_err(dev, "failed to reserve memory space for MSI\n"); > > err = -ENOMEM; > > diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c > > index 1cfe368..4768d54 100644 > > --- a/drivers/pci/endpoint/functions/pci-epf-test.c > > +++ b/drivers/pci/endpoint/functions/pci-epf-test.c > > @@ -84,8 +84,14 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) > > struct pci_epc *epc = epf->epc; > > enum pci_barno test_reg_bar = epf_test->test_reg_bar; > > struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; > > - > > - src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size); > > + int window; > > + > > + src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, > > + &window, reg->size, > > + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | > > + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | > > + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | > > + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); > > if (!src_addr) { > > dev_err(dev, "Failed to allocate source address\n"); > > reg->status = STATUS_SRC_ADDR_INVALID; > > @@ -93,15 +99,20 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) > > goto err; > > } > > > > - ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, reg->src_addr, > > - reg->size); > > + ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, window, > > + reg->src_addr, reg->size); > > if (ret) { > > dev_err(dev, "Failed to map source address\n"); > > reg->status = STATUS_SRC_ADDR_INVALID; > > goto err_src_addr; > > } > > > > - dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size); > > + dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, > > + &window, reg->size, > > + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | > > + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | > > + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | > > + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); > > if (!dst_addr) { > > dev_err(dev, "Failed to allocate destination address\n"); > > reg->status = STATUS_DST_ADDR_INVALID; > > @@ -109,8 +120,8 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) > > goto err_src_map_addr; > > } > > > > - ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, reg->dst_addr, > > - reg->size); > > + ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, window, > > + reg->dst_addr, reg->size); > > if (ret) { > > dev_err(dev, "Failed to map destination address\n"); > > reg->status = STATUS_DST_ADDR_INVALID; > > @@ -146,8 +157,13 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test) > > struct pci_epc *epc = epf->epc; > > enum pci_barno test_reg_bar = epf_test->test_reg_bar; > > struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; > > + int window; > > > > - src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); > > + src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, &window, reg->size, > > + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | > > + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | > > + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | > > + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); > > if (!src_addr) { > > dev_err(dev, "Failed to allocate address\n"); > > reg->status = STATUS_SRC_ADDR_INVALID; > > @@ -155,8 +171,8 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test) > > goto err; > > } > > > > - ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->src_addr, > > - reg->size); > > + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, window, > > + reg->src_addr, reg->size); > > if (ret) { > > dev_err(dev, "Failed to map address\n"); > > reg->status = STATUS_SRC_ADDR_INVALID; > > @@ -193,13 +209,18 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test) > > void __iomem *dst_addr; > > void *buf; > > phys_addr_t phys_addr; > > + int window; > > struct pci_epf *epf = epf_test->epf; > > struct device *dev = &epf->dev; > > struct pci_epc *epc = epf->epc; > > enum pci_barno test_reg_bar = epf_test->test_reg_bar; > > struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; > > > > - dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); > > + dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, &window, reg->size, > > + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | > > + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | > > + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | > > + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); > > if (!dst_addr) { > > dev_err(dev, "Failed to allocate address\n"); > > reg->status = STATUS_DST_ADDR_INVALID; > > @@ -207,8 +228,8 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test) > > goto err; > > } > > > > - ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->dst_addr, > > - reg->size); > > + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, window, > > + reg->dst_addr, reg->size); > > if (ret) { > > dev_err(dev, "Failed to map address\n"); > > reg->status = STATUS_DST_ADDR_INVALID; > > diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c > > index 2091508..289c266 100644 > > --- a/drivers/pci/endpoint/pci-epc-core.c > > +++ b/drivers/pci/endpoint/pci-epc-core.c > > @@ -358,13 +358,15 @@ EXPORT_SYMBOL_GPL(pci_epc_unmap_addr); > > * @epc: the EPC device on which address is allocated > > * @func_no: the endpoint function number in the EPC device > > * @phys_addr: physical address of the local system > > + * @window: index to the window region where PCI address will be mapped > > * @pci_addr: PCI address to which the physical address should be mapped > > * @size: the size of the allocation > > * > > * Invoke to map CPU address with PCI address. > > */ > > int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, > > - phys_addr_t phys_addr, u64 pci_addr, size_t size) > > + phys_addr_t phys_addr, int window, > > + u64 pci_addr, size_t size) > > { > > int ret; > > unsigned long flags; > > @@ -376,7 +378,8 @@ int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, > > return 0; > > > > spin_lock_irqsave(&epc->lock, flags); > > - ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size); > > + ret = epc->ops->map_addr(epc, func_no, phys_addr, > > + window, pci_addr, size); > > spin_unlock_irqrestore(&epc->lock, flags); > > > > return ret; > > diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c > > index 2bf8bd1..4b610cd 100644 > > --- a/drivers/pci/endpoint/pci-epc-mem.c > > +++ b/drivers/pci/endpoint/pci-epc-mem.c > > @@ -39,56 +39,78 @@ static int pci_epc_mem_get_order(struct pci_epc_mem *mem, size_t size) > > * __pci_epc_mem_init() - initialize the pci_epc_mem structure > > * @epc: the EPC device that invoked pci_epc_mem_init > > * @phys_base: the physical address of the base > > - * @size: the size of the address space > > + * @num_windows: number of windows device supports > > * @page_size: size of each page > > * > > * Invoke to initialize the pci_epc_mem structure used by the > > * endpoint functions to allocate mapped PCI address. > > */ > > -int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_base, size_t size, > > - size_t page_size) > > +int __pci_epc_mem_init(struct pci_epc *epc, struct pci_epc_mem_window *windows, > > + int num_windows, size_t page_size) > > { > > - int ret; > > - struct pci_epc_mem *mem; > > - unsigned long *bitmap; > > + struct pci_epc_mem *mem = NULL; > > + unsigned long *bitmap = NULL; > > unsigned int page_shift; > > - int pages; > > int bitmap_size; > > + int pages; > > + int ret; > > + int i; > > + > > + epc->mem_windows = 0; > > + > > + if (!windows) > > + return -EINVAL; > > + > > + if (num_windows <= 0) > > + return -EINVAL; > > > > if (page_size < PAGE_SIZE) > > page_size = PAGE_SIZE; > > > > page_shift = ilog2(page_size); > > - pages = size >> page_shift; > > - bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); > > > > - mem = kzalloc(sizeof(*mem), GFP_KERNEL); > > - if (!mem) { > > - ret = -ENOMEM; > > - goto err; > > - } > > + epc->mem = kcalloc(num_windows, sizeof(*mem), GFP_KERNEL); > > + if (!epc->mem) > > + return -EINVAL; > > > > - bitmap = kzalloc(bitmap_size, GFP_KERNEL); > > - if (!bitmap) { > > - ret = -ENOMEM; > > - goto err_mem; > > - } > > + for (i = 0; i < num_windows; i++) { > > + pages = windows[i].phys_base >> page_shift; > > + bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); > > > > - mem->bitmap = bitmap; > > - mem->phys_base = phys_base; > > - mem->page_size = page_size; > > - mem->pages = pages; > > - mem->size = size; > > + mem = kzalloc(sizeof(*mem), GFP_KERNEL); > > + if (!mem) { > > + ret = -ENOMEM; > > + goto err_mem; > > + } > > > > - epc->mem = mem; > > + bitmap = kzalloc(bitmap_size, GFP_KERNEL); > > + if (!bitmap) { > > + ret = -ENOMEM; > > + goto err_mem; > > + } > > + > > + mem->bitmap = bitmap; > > + mem->window.phys_base = windows[i].phys_base; > > + mem->page_size = page_size; > > + mem->pages = pages; > > + mem->window.size = windows[i].size; > > + mem->window.map_size = 0; > > + mem->window.flags = windows[i].flags; > > + > > + epc->mem[i] = mem; > > + } > > + epc->mem_windows = num_windows; > > > > return 0; > > > > err_mem: > > - kfree(mem); > > + for (; i >= 0; i--) { > > + kfree(mem->bitmap); > > + kfree(epc->mem[i]); > > + } > > + kfree(epc->mem); > > > > -err: > > -return ret; > > + return ret; > > } > > EXPORT_SYMBOL_GPL(__pci_epc_mem_init); > > > > @@ -101,48 +123,152 @@ EXPORT_SYMBOL_GPL(__pci_epc_mem_init); > > */ > > void pci_epc_mem_exit(struct pci_epc *epc) > > { > > - struct pci_epc_mem *mem = epc->mem; > > + struct pci_epc_mem *mem; > > + int i; > > + > > + if (!epc->mem_windows) > > + return; > > + > > + for (i = 0; i <= epc->mem_windows; i--) { > > + mem = epc->mem[i]; > > + kfree(mem->bitmap); > > + kfree(epc->mem[i]); > > + } > > + kfree(epc->mem); > > > > epc->mem = NULL; > > - kfree(mem->bitmap); > > - kfree(mem); > > + epc->mem_windows = 0; > > } > > EXPORT_SYMBOL_GPL(pci_epc_mem_exit); > > > > +static int pci_epc_find_best_fit_window(struct pci_epc *epc, size_t size, > > + u32 flags) > > +{ > > + size_t window_least_size = 0; > > + int best_fit_window = -1; > > + struct pci_epc_mem *mem; > > + size_t actual_size; > > + size_t avail_size; > > + u32 win_flags; > > + int i; > > + > > + for (i = 0; i < epc->mem_windows; i++) { > > + mem = epc->mem[i]; > > + win_flags = mem->window.flags; > > + > > + actual_size = ALIGN(size, mem->page_size); > > + avail_size = mem->window.size - mem->window.map_size; > > + > > + if (win_flags == 0x0) { > > + if (best_fit_window == -1) { > > + if (actual_size <= avail_size) { > > + best_fit_window = i; > > + window_least_size = mem->window.size; > > + } > > + } else { > > + if (actual_size <= avail_size && > > + mem->window.size < window_least_size) { > > + best_fit_window = i; > > + window_least_size = mem->window.size; > > + } > > + } > > + } else { > > + if (mem->window.map_size && > > + (win_flags | PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC)) > > + continue; > > + > > + if (!(win_flags | flags)) > > + continue; > > + > > + if (best_fit_window == -1) { > > + if (actual_size <= avail_size) { > > + best_fit_window = i; > > + window_least_size = mem->window.size; > > + } > > + } else { > > + if (actual_size <= avail_size && > > + mem->window.size < window_least_size) { > > + best_fit_window = i; > > + window_least_size = mem->window.size; > > + } > > + } > > + } > > + } > > + > > + return best_fit_window; > > +} > > + > > /** > > * pci_epc_mem_alloc_addr() - allocate memory address from EPC addr space > > * @epc: the EPC device on which memory has to be allocated > > * @phys_addr: populate the allocated physical address here > > + * @window: populate the window here which will be used to map PCI address > > * @size: the size of the address space that has to be allocated > > + * @flags: look for window as requested in flags > > * > > * Invoke to allocate memory address from the EPC address space. This > > * is usually done to map the remote RC address into the local system. > > */ > > void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, > > - phys_addr_t *phys_addr, size_t size) > > + phys_addr_t *phys_addr, > > + int *window, size_t size, uint32_t flags) > > { > > + int best_fit = PCI_EPC_DEFAULT_WINDOW; > > + void __iomem *virt_addr = NULL; > > + struct pci_epc_mem *mem; > > + unsigned int page_shift; > > int pageno; > > - void __iomem *virt_addr; > > - struct pci_epc_mem *mem = epc->mem; > > - unsigned int page_shift = ilog2(mem->page_size); > > int order; > > > > + if (epc->mem_windows <= 0) > > + return NULL; > > + > > + if (epc->mem_windows > 1) { > > + best_fit = pci_epc_find_best_fit_window(epc, size, flags); > > + if (best_fit < 0) > > + return NULL; > > + } > > + > > + mem = epc->mem[best_fit]; > > size = ALIGN(size, mem->page_size); > > + if (size > (mem->window.size - mem->window.map_size)) > > + return NULL; > > + page_shift = ilog2(mem->page_size); > > order = pci_epc_mem_get_order(mem, size); > > > > pageno = bitmap_find_free_region(mem->bitmap, mem->pages, order); > > if (pageno < 0) > > return NULL; > > > > - *phys_addr = mem->phys_base + (pageno << page_shift); > > + *phys_addr = mem->window.phys_base + (pageno << page_shift); > > virt_addr = ioremap(*phys_addr, size); > > - if (!virt_addr) > > + if (!virt_addr) { > > bitmap_release_region(mem->bitmap, pageno, order); > > + } else { > > + mem->window.map_size += size; > > + *window = best_fit; > > + } > > > > return virt_addr; > > } > > EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); > > > > +static int pci_epc_get_matching_window(struct pci_epc *epc, > > + phys_addr_t phys_addr) > > +{ > > + struct pci_epc_mem *mem; > > + int i; > > + > > + for (i = 0; i < epc->mem_windows; i++) { > > + mem = epc->mem[i]; > > + > > + if (mem->window.phys_base == phys_addr) > > + return i; > > + } > > + > > + return -EINVAL; > > +} > > + > > /** > > * pci_epc_mem_free_addr() - free the allocated memory address > > * @epc: the EPC device on which memory was allocated > > @@ -155,16 +281,26 @@ EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); > > void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr, > > void __iomem *virt_addr, size_t size) > > { > > + struct pci_epc_mem *mem; > > + unsigned int page_shift; > > + int window = 0; > > int pageno; > > - struct pci_epc_mem *mem = epc->mem; > > - unsigned int page_shift = ilog2(mem->page_size); > > int order; > > > > + if (epc->mem_windows > 1) { > > + window = pci_epc_get_matching_window(epc, phys_addr); > > + if (window < 0) > > + return; > > + } > > + > > + mem = epc->mem[window]; > > + page_shift = ilog2(mem->page_size); > > iounmap(virt_addr); > > - pageno = (phys_addr - mem->phys_base) >> page_shift; > > + pageno = (phys_addr - mem->window.phys_base) >> page_shift; > > size = ALIGN(size, mem->page_size); > > order = pci_epc_mem_get_order(mem, size); > > bitmap_release_region(mem->bitmap, pageno, order); > > + mem->window.map_size -= size; > > } > > EXPORT_SYMBOL_GPL(pci_epc_mem_free_addr); > > > > diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h > > index f641bad..bee6f65 100644 > > --- a/include/linux/pci-epc.h > > +++ b/include/linux/pci-epc.h > > @@ -48,7 +48,8 @@ struct pci_epc_ops { > > void (*clear_bar)(struct pci_epc *epc, u8 func_no, > > struct pci_epf_bar *epf_bar); > > int (*map_addr)(struct pci_epc *epc, u8 func_no, > > - phys_addr_t addr, u64 pci_addr, size_t size); > > + phys_addr_t addr, int window, > > + u64 pci_addr, size_t size); > > void (*unmap_addr)(struct pci_epc *epc, u8 func_no, > > phys_addr_t addr); > > int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts); > > @@ -64,17 +65,57 @@ struct pci_epc_ops { > > struct module *owner; > > }; > > > > +#define PCI_EPC_DEFAULT_WINDOW 0 > > + > > +/** > > + * enum pci_epc_window_flags - flags info for pci_epc_mem_window > > + * > > + * This enum defines how the endpoint controller window should be used > > + * for allocations. > > + * > > + * @PCI_EPC_WINDOW_FLAG_MULTI_ALLOC: Indicates multiple chunks of memory can be > > + * allocated from same window > > + * @PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC: Indicates only single memory allocation > > + * is possible on the window > > Instead of NON_MULTI_ALLOC, we could simply have different page_size for > different windows. For a platform that doesn't allow multiple alloc, > page size will be equal to the window size. > I would still prefer this flag and not go with page size = window size as we could allocate unnecessary memory that might not be used and also the window sizes might be too large. > > + * @PCI_EPC_WINDOW_FLAG_LARGE_ALLOC: Window is used for large memory allocation > > + * @PCI_EPC_WINDOW_FLAG_SMALL_ALLOC: Window is used for small memory allocation > > + * @PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC: Window is used for high priority data > > + * transfers > > + * @PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC: Window is used for low priority data > > + * transfers > > Let's defer adding these flags until a platform actually starts to use this. > sure will drop the above. Cheers, --Prabhakar > Thanks > Kishon ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 2/6] pci: endpoint: add support to handle features of outbound memory 2019-12-18 17:23 ` Lad, Prabhakar @ 2020-01-02 9:44 ` Kishon Vijay Abraham I 2020-01-02 9:59 ` Lad, Prabhakar 0 siblings, 1 reply; 27+ messages in thread From: Kishon Vijay Abraham I @ 2020-01-02 9:44 UTC (permalink / raw) To: Lad, Prabhakar Cc: Bjorn Helgaas, Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Marek Vasut, Yoshihiro Shimoda, linux-pci, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML, LAK, Linux-Renesas, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, open list:ARM/Rockchip SoC..., Lad, Prabhakar Hi Prabhakar, On 18/12/19 10:53 PM, Lad, Prabhakar wrote: > Hi Kishon, > > On Mon, Dec 16, 2019 at 11:34 AM Kishon Vijay Abraham I <kishon@ti.com> wrote: >> >> Hi Prabhakar, >> >> On 13/12/19 2:17 pm, wrote: >>> From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> >>> >>> rcar pcie controller has support to map multiple memory regions >>> for mapping the outbound memory in local system, this feature >>> inspires to add support for handling such features in endpoint >>> framework. similar features exists on other controllers where >>> outbound regions can be specifically used for low/high priority >>> transactions, and regions can be flagged and used for allocation >>> of large/small memory allocations. >>> This patch adds support to handle such features, where the >>> properties described for outbound regions are used whenever a >>> request to memory is made. >>> >>> Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> >>> --- >>> drivers/pci/controller/dwc/pcie-designware-ep.c | 30 ++-- >>> drivers/pci/controller/pcie-cadence-ep.c | 11 +- >>> drivers/pci/controller/pcie-rockchip-ep.c | 13 +- >>> drivers/pci/endpoint/functions/pci-epf-test.c | 47 ++++-- >>> drivers/pci/endpoint/pci-epc-core.c | 7 +- >>> drivers/pci/endpoint/pci-epc-mem.c | 216 +++++++++++++++++++----- >>> include/linux/pci-epc.h | 72 ++++++-- >>> 7 files changed, 307 insertions(+), 89 deletions(-) >>> >>> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c >>> index 3dd2e26..be6aa94 100644 >>> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c >>> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c >>> @@ -195,7 +195,7 @@ static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no, >>> } >>> >>> static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, >>> - phys_addr_t addr, >>> + phys_addr_t addr, int window, >>> u64 pci_addr, size_t size) >>> { >>> int ret; >>> @@ -367,6 +367,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, >>> unsigned int aligned_offset; >>> u16 msg_ctrl, msg_data; >>> u32 msg_addr_lower, msg_addr_upper, reg; >>> + int window = PCI_EPC_DEFAULT_WINDOW; >>> u64 msg_addr; >>> bool has_upper; >>> int ret; >>> @@ -390,11 +391,11 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, >>> reg = ep->msi_cap + PCI_MSI_DATA_32; >>> msg_data = dw_pcie_readw_dbi(pci, reg); >>> } >>> - aligned_offset = msg_addr_lower & (epc->mem->page_size - 1); >>> + aligned_offset = msg_addr_lower & (epc->mem[window]->page_size - 1); >>> msg_addr = ((u64)msg_addr_upper) << 32 | >>> (msg_addr_lower & ~aligned_offset); >>> - ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, >>> - epc->mem->page_size); >>> + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, window, >>> + msg_addr, epc->mem[window]->page_size); >>> if (ret) >>> return ret; >>> >>> @@ -416,6 +417,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, >>> u32 reg, msg_data, vec_ctrl; >>> u64 tbl_addr, msg_addr, reg_u64; >>> void __iomem *msix_tbl; >>> + int window = PCI_EPC_DEFAULT_WINDOW; >>> int ret; >>> >>> reg = ep->msix_cap + PCI_MSIX_TABLE; >>> @@ -452,8 +454,8 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, >>> return -EPERM; >>> } >>> >>> - ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, >>> - epc->mem->page_size); >>> + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, window, >>> + msg_addr, epc->mem[window]->page_size); >>> if (ret) >>> return ret; >>> >>> @@ -466,10 +468,11 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, >>> >>> void dw_pcie_ep_exit(struct dw_pcie_ep *ep) >>> { >>> + int window = PCI_EPC_DEFAULT_WINDOW; >>> struct pci_epc *epc = ep->epc; >>> >>> pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, >>> - epc->mem->page_size); >>> + epc->mem[window]->page_size); >>> >>> pci_epc_mem_exit(epc); >>> } >>> @@ -499,9 +502,12 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) >>> u32 reg; >>> void *addr; >>> u8 hdr_type; >>> + int window; >>> unsigned int nbars; >>> unsigned int offset; >>> struct pci_epc *epc; >>> + size_t msi_page_size; >>> + struct pci_epc_mem_window mem_window; >>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep); >>> struct device *dev = pci->dev; >>> struct device_node *np = dev->of_node; >>> @@ -574,15 +580,17 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) >>> if (ret < 0) >>> epc->max_functions = 1; >>> >>> - ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, >>> - ep->page_size); >>> + mem_window.phys_base = ep->phys_base; >>> + mem_window.size = ep->addr_size; >>> + ret = __pci_epc_mem_init(epc, &mem_window, 1, ep->page_size); >>> if (ret < 0) { >>> dev_err(dev, "Failed to initialize address space\n"); >>> return ret; >>> } >>> >>> - ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, >>> - epc->mem->page_size); >>> + msi_page_size = epc->mem[PCI_EPC_DEFAULT_WINDOW]->page_size; >>> + ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, &window, >>> + msi_page_size, 0x0); >>> if (!ep->msi_mem) { >>> dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); >>> return -ENOMEM; >>> diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c >>> index def7820..2410706 100644 >>> --- a/drivers/pci/controller/pcie-cadence-ep.c >>> +++ b/drivers/pci/controller/pcie-cadence-ep.c >>> @@ -172,7 +172,7 @@ static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, >>> } >>> >>> static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr, >>> - u64 pci_addr, size_t size) >>> + int window, u64 pci_addr, size_t size) >>> { >>> struct cdns_pcie_ep *ep = epc_get_drvdata(epc); >>> struct cdns_pcie *pcie = &ep->pcie; >>> @@ -434,12 +434,14 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) >>> { >>> struct device *dev = &pdev->dev; >>> struct device_node *np = dev->of_node; >>> + struct pci_epc_mem_window mem_window; >>> struct cdns_pcie_ep *ep; >>> struct cdns_pcie *pcie; >>> struct pci_epc *epc; >>> struct resource *res; >>> int ret; >>> int phy_count; >>> + int window; >>> >>> ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); >>> if (!ep) >>> @@ -502,15 +504,16 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) >>> if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) >>> epc->max_functions = 1; >>> >>> - ret = pci_epc_mem_init(epc, pcie->mem_res->start, >>> - resource_size(pcie->mem_res)); >>> + mem_window.phys_base = pcie->mem_res->start; >>> + mem_window.size = resource_size(pcie->mem_res); >>> + ret = pci_epc_mem_init(epc, &mem_window, 1); >>> if (ret < 0) { >>> dev_err(dev, "failed to initialize the memory space\n"); >>> goto err_init; >>> } >>> >>> ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, >>> - SZ_128K); >>> + &window, SZ_128K, 0x0); >>> if (!ep->irq_cpu_addr) { >>> dev_err(dev, "failed to reserve memory space for MSI\n"); >>> ret = -ENOMEM; >>> diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c >>> index d743b0a..828052c 100644 >>> --- a/drivers/pci/controller/pcie-rockchip-ep.c >>> +++ b/drivers/pci/controller/pcie-rockchip-ep.c >>> @@ -256,8 +256,8 @@ static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, >>> } >>> >>> static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, >>> - phys_addr_t addr, u64 pci_addr, >>> - size_t size) >>> + phys_addr_t addr, int window, >>> + u64 pci_addr, size_t size) >>> { >>> struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); >>> struct rockchip_pcie *pcie = &ep->rockchip; >>> @@ -562,11 +562,13 @@ static const struct of_device_id rockchip_pcie_ep_of_match[] = { >>> >>> static int rockchip_pcie_ep_probe(struct platform_device *pdev) >>> { >>> + struct pci_epc_mem_window mem_window; >>> struct device *dev = &pdev->dev; >>> struct rockchip_pcie_ep *ep; >>> struct rockchip_pcie *rockchip; >>> struct pci_epc *epc; >>> size_t max_regions; >>> + int window; >>> int err; >>> >>> ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); >>> @@ -614,15 +616,16 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) >>> /* Only enable function 0 by default */ >>> rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); >>> >>> - err = pci_epc_mem_init(epc, rockchip->mem_res->start, >>> - resource_size(rockchip->mem_res)); >>> + mem_window.phys_base = rockchip->mem_res->start; >>> + mem_window.size = resource_size(rockchip->mem_res); >>> + err = pci_epc_mem_init(epc, &mem_window, 1); >>> if (err < 0) { >>> dev_err(dev, "failed to initialize the memory space\n"); >>> goto err_uninit_port; >>> } >>> >>> ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, >>> - SZ_128K); >>> + &window, SZ_128K, 0x0); >>> if (!ep->irq_cpu_addr) { >>> dev_err(dev, "failed to reserve memory space for MSI\n"); >>> err = -ENOMEM; >>> diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c >>> index 1cfe368..4768d54 100644 >>> --- a/drivers/pci/endpoint/functions/pci-epf-test.c >>> +++ b/drivers/pci/endpoint/functions/pci-epf-test.c >>> @@ -84,8 +84,14 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) >>> struct pci_epc *epc = epf->epc; >>> enum pci_barno test_reg_bar = epf_test->test_reg_bar; >>> struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; >>> - >>> - src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size); >>> + int window; >>> + >>> + src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, >>> + &window, reg->size, >>> + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | >>> + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | >>> + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | >>> + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); >>> if (!src_addr) { >>> dev_err(dev, "Failed to allocate source address\n"); >>> reg->status = STATUS_SRC_ADDR_INVALID; >>> @@ -93,15 +99,20 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) >>> goto err; >>> } >>> >>> - ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, reg->src_addr, >>> - reg->size); >>> + ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, window, >>> + reg->src_addr, reg->size); >>> if (ret) { >>> dev_err(dev, "Failed to map source address\n"); >>> reg->status = STATUS_SRC_ADDR_INVALID; >>> goto err_src_addr; >>> } >>> >>> - dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size); >>> + dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, >>> + &window, reg->size, >>> + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | >>> + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | >>> + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | >>> + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); >>> if (!dst_addr) { >>> dev_err(dev, "Failed to allocate destination address\n"); >>> reg->status = STATUS_DST_ADDR_INVALID; >>> @@ -109,8 +120,8 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) >>> goto err_src_map_addr; >>> } >>> >>> - ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, reg->dst_addr, >>> - reg->size); >>> + ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, window, >>> + reg->dst_addr, reg->size); >>> if (ret) { >>> dev_err(dev, "Failed to map destination address\n"); >>> reg->status = STATUS_DST_ADDR_INVALID; >>> @@ -146,8 +157,13 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test) >>> struct pci_epc *epc = epf->epc; >>> enum pci_barno test_reg_bar = epf_test->test_reg_bar; >>> struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; >>> + int window; >>> >>> - src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); >>> + src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, &window, reg->size, >>> + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | >>> + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | >>> + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | >>> + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); >>> if (!src_addr) { >>> dev_err(dev, "Failed to allocate address\n"); >>> reg->status = STATUS_SRC_ADDR_INVALID; >>> @@ -155,8 +171,8 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test) >>> goto err; >>> } >>> >>> - ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->src_addr, >>> - reg->size); >>> + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, window, >>> + reg->src_addr, reg->size); >>> if (ret) { >>> dev_err(dev, "Failed to map address\n"); >>> reg->status = STATUS_SRC_ADDR_INVALID; >>> @@ -193,13 +209,18 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test) >>> void __iomem *dst_addr; >>> void *buf; >>> phys_addr_t phys_addr; >>> + int window; >>> struct pci_epf *epf = epf_test->epf; >>> struct device *dev = &epf->dev; >>> struct pci_epc *epc = epf->epc; >>> enum pci_barno test_reg_bar = epf_test->test_reg_bar; >>> struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; >>> >>> - dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); >>> + dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, &window, reg->size, >>> + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | >>> + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | >>> + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | >>> + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); >>> if (!dst_addr) { >>> dev_err(dev, "Failed to allocate address\n"); >>> reg->status = STATUS_DST_ADDR_INVALID; >>> @@ -207,8 +228,8 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test) >>> goto err; >>> } >>> >>> - ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->dst_addr, >>> - reg->size); >>> + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, window, >>> + reg->dst_addr, reg->size); >>> if (ret) { >>> dev_err(dev, "Failed to map address\n"); >>> reg->status = STATUS_DST_ADDR_INVALID; >>> diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c >>> index 2091508..289c266 100644 >>> --- a/drivers/pci/endpoint/pci-epc-core.c >>> +++ b/drivers/pci/endpoint/pci-epc-core.c >>> @@ -358,13 +358,15 @@ EXPORT_SYMBOL_GPL(pci_epc_unmap_addr); >>> * @epc: the EPC device on which address is allocated >>> * @func_no: the endpoint function number in the EPC device >>> * @phys_addr: physical address of the local system >>> + * @window: index to the window region where PCI address will be mapped >>> * @pci_addr: PCI address to which the physical address should be mapped >>> * @size: the size of the allocation >>> * >>> * Invoke to map CPU address with PCI address. >>> */ >>> int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, >>> - phys_addr_t phys_addr, u64 pci_addr, size_t size) >>> + phys_addr_t phys_addr, int window, >>> + u64 pci_addr, size_t size) >>> { >>> int ret; >>> unsigned long flags; >>> @@ -376,7 +378,8 @@ int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, >>> return 0; >>> >>> spin_lock_irqsave(&epc->lock, flags); >>> - ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size); >>> + ret = epc->ops->map_addr(epc, func_no, phys_addr, >>> + window, pci_addr, size); >>> spin_unlock_irqrestore(&epc->lock, flags); >>> >>> return ret; >>> diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c >>> index 2bf8bd1..4b610cd 100644 >>> --- a/drivers/pci/endpoint/pci-epc-mem.c >>> +++ b/drivers/pci/endpoint/pci-epc-mem.c >>> @@ -39,56 +39,78 @@ static int pci_epc_mem_get_order(struct pci_epc_mem *mem, size_t size) >>> * __pci_epc_mem_init() - initialize the pci_epc_mem structure >>> * @epc: the EPC device that invoked pci_epc_mem_init >>> * @phys_base: the physical address of the base >>> - * @size: the size of the address space >>> + * @num_windows: number of windows device supports >>> * @page_size: size of each page >>> * >>> * Invoke to initialize the pci_epc_mem structure used by the >>> * endpoint functions to allocate mapped PCI address. >>> */ >>> -int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_base, size_t size, >>> - size_t page_size) >>> +int __pci_epc_mem_init(struct pci_epc *epc, struct pci_epc_mem_window *windows, >>> + int num_windows, size_t page_size) >>> { >>> - int ret; >>> - struct pci_epc_mem *mem; >>> - unsigned long *bitmap; >>> + struct pci_epc_mem *mem = NULL; >>> + unsigned long *bitmap = NULL; >>> unsigned int page_shift; >>> - int pages; >>> int bitmap_size; >>> + int pages; >>> + int ret; >>> + int i; >>> + >>> + epc->mem_windows = 0; >>> + >>> + if (!windows) >>> + return -EINVAL; >>> + >>> + if (num_windows <= 0) >>> + return -EINVAL; >>> >>> if (page_size < PAGE_SIZE) >>> page_size = PAGE_SIZE; >>> >>> page_shift = ilog2(page_size); >>> - pages = size >> page_shift; >>> - bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); >>> >>> - mem = kzalloc(sizeof(*mem), GFP_KERNEL); >>> - if (!mem) { >>> - ret = -ENOMEM; >>> - goto err; >>> - } >>> + epc->mem = kcalloc(num_windows, sizeof(*mem), GFP_KERNEL); >>> + if (!epc->mem) >>> + return -EINVAL; >>> >>> - bitmap = kzalloc(bitmap_size, GFP_KERNEL); >>> - if (!bitmap) { >>> - ret = -ENOMEM; >>> - goto err_mem; >>> - } >>> + for (i = 0; i < num_windows; i++) { >>> + pages = windows[i].phys_base >> page_shift; >>> + bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); >>> >>> - mem->bitmap = bitmap; >>> - mem->phys_base = phys_base; >>> - mem->page_size = page_size; >>> - mem->pages = pages; >>> - mem->size = size; >>> + mem = kzalloc(sizeof(*mem), GFP_KERNEL); >>> + if (!mem) { >>> + ret = -ENOMEM; >>> + goto err_mem; >>> + } >>> >>> - epc->mem = mem; >>> + bitmap = kzalloc(bitmap_size, GFP_KERNEL); >>> + if (!bitmap) { >>> + ret = -ENOMEM; >>> + goto err_mem; >>> + } >>> + >>> + mem->bitmap = bitmap; >>> + mem->window.phys_base = windows[i].phys_base; >>> + mem->page_size = page_size; >>> + mem->pages = pages; >>> + mem->window.size = windows[i].size; >>> + mem->window.map_size = 0; >>> + mem->window.flags = windows[i].flags; >>> + >>> + epc->mem[i] = mem; >>> + } >>> + epc->mem_windows = num_windows; >>> >>> return 0; >>> >>> err_mem: >>> - kfree(mem); >>> + for (; i >= 0; i--) { >>> + kfree(mem->bitmap); >>> + kfree(epc->mem[i]); >>> + } >>> + kfree(epc->mem); >>> >>> -err: >>> -return ret; >>> + return ret; >>> } >>> EXPORT_SYMBOL_GPL(__pci_epc_mem_init); >>> >>> @@ -101,48 +123,152 @@ EXPORT_SYMBOL_GPL(__pci_epc_mem_init); >>> */ >>> void pci_epc_mem_exit(struct pci_epc *epc) >>> { >>> - struct pci_epc_mem *mem = epc->mem; >>> + struct pci_epc_mem *mem; >>> + int i; >>> + >>> + if (!epc->mem_windows) >>> + return; >>> + >>> + for (i = 0; i <= epc->mem_windows; i--) { >>> + mem = epc->mem[i]; >>> + kfree(mem->bitmap); >>> + kfree(epc->mem[i]); >>> + } >>> + kfree(epc->mem); >>> >>> epc->mem = NULL; >>> - kfree(mem->bitmap); >>> - kfree(mem); >>> + epc->mem_windows = 0; >>> } >>> EXPORT_SYMBOL_GPL(pci_epc_mem_exit); >>> >>> +static int pci_epc_find_best_fit_window(struct pci_epc *epc, size_t size, >>> + u32 flags) >>> +{ >>> + size_t window_least_size = 0; >>> + int best_fit_window = -1; >>> + struct pci_epc_mem *mem; >>> + size_t actual_size; >>> + size_t avail_size; >>> + u32 win_flags; >>> + int i; >>> + >>> + for (i = 0; i < epc->mem_windows; i++) { >>> + mem = epc->mem[i]; >>> + win_flags = mem->window.flags; >>> + >>> + actual_size = ALIGN(size, mem->page_size); >>> + avail_size = mem->window.size - mem->window.map_size; >>> + >>> + if (win_flags == 0x0) { >>> + if (best_fit_window == -1) { >>> + if (actual_size <= avail_size) { >>> + best_fit_window = i; >>> + window_least_size = mem->window.size; >>> + } >>> + } else { >>> + if (actual_size <= avail_size && >>> + mem->window.size < window_least_size) { >>> + best_fit_window = i; >>> + window_least_size = mem->window.size; >>> + } >>> + } >>> + } else { >>> + if (mem->window.map_size && >>> + (win_flags | PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC)) >>> + continue; >>> + >>> + if (!(win_flags | flags)) >>> + continue; >>> + >>> + if (best_fit_window == -1) { >>> + if (actual_size <= avail_size) { >>> + best_fit_window = i; >>> + window_least_size = mem->window.size; >>> + } >>> + } else { >>> + if (actual_size <= avail_size && >>> + mem->window.size < window_least_size) { >>> + best_fit_window = i; >>> + window_least_size = mem->window.size; >>> + } >>> + } >>> + } >>> + } >>> + >>> + return best_fit_window; >>> +} >>> + >>> /** >>> * pci_epc_mem_alloc_addr() - allocate memory address from EPC addr space >>> * @epc: the EPC device on which memory has to be allocated >>> * @phys_addr: populate the allocated physical address here >>> + * @window: populate the window here which will be used to map PCI address >>> * @size: the size of the address space that has to be allocated >>> + * @flags: look for window as requested in flags >>> * >>> * Invoke to allocate memory address from the EPC address space. This >>> * is usually done to map the remote RC address into the local system. >>> */ >>> void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, >>> - phys_addr_t *phys_addr, size_t size) >>> + phys_addr_t *phys_addr, >>> + int *window, size_t size, uint32_t flags) >>> { >>> + int best_fit = PCI_EPC_DEFAULT_WINDOW; >>> + void __iomem *virt_addr = NULL; >>> + struct pci_epc_mem *mem; >>> + unsigned int page_shift; >>> int pageno; >>> - void __iomem *virt_addr; >>> - struct pci_epc_mem *mem = epc->mem; >>> - unsigned int page_shift = ilog2(mem->page_size); >>> int order; >>> >>> + if (epc->mem_windows <= 0) >>> + return NULL; >>> + >>> + if (epc->mem_windows > 1) { >>> + best_fit = pci_epc_find_best_fit_window(epc, size, flags); >>> + if (best_fit < 0) >>> + return NULL; >>> + } >>> + >>> + mem = epc->mem[best_fit]; >>> size = ALIGN(size, mem->page_size); >>> + if (size > (mem->window.size - mem->window.map_size)) >>> + return NULL; >>> + page_shift = ilog2(mem->page_size); >>> order = pci_epc_mem_get_order(mem, size); >>> >>> pageno = bitmap_find_free_region(mem->bitmap, mem->pages, order); >>> if (pageno < 0) >>> return NULL; >>> >>> - *phys_addr = mem->phys_base + (pageno << page_shift); >>> + *phys_addr = mem->window.phys_base + (pageno << page_shift); >>> virt_addr = ioremap(*phys_addr, size); >>> - if (!virt_addr) >>> + if (!virt_addr) { >>> bitmap_release_region(mem->bitmap, pageno, order); >>> + } else { >>> + mem->window.map_size += size; >>> + *window = best_fit; >>> + } >>> >>> return virt_addr; >>> } >>> EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); >>> >>> +static int pci_epc_get_matching_window(struct pci_epc *epc, >>> + phys_addr_t phys_addr) >>> +{ >>> + struct pci_epc_mem *mem; >>> + int i; >>> + >>> + for (i = 0; i < epc->mem_windows; i++) { >>> + mem = epc->mem[i]; >>> + >>> + if (mem->window.phys_base == phys_addr) >>> + return i; >>> + } >>> + >>> + return -EINVAL; >>> +} >>> + >>> /** >>> * pci_epc_mem_free_addr() - free the allocated memory address >>> * @epc: the EPC device on which memory was allocated >>> @@ -155,16 +281,26 @@ EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); >>> void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr, >>> void __iomem *virt_addr, size_t size) >>> { >>> + struct pci_epc_mem *mem; >>> + unsigned int page_shift; >>> + int window = 0; >>> int pageno; >>> - struct pci_epc_mem *mem = epc->mem; >>> - unsigned int page_shift = ilog2(mem->page_size); >>> int order; >>> >>> + if (epc->mem_windows > 1) { >>> + window = pci_epc_get_matching_window(epc, phys_addr); >>> + if (window < 0) >>> + return; >>> + } >>> + >>> + mem = epc->mem[window]; >>> + page_shift = ilog2(mem->page_size); >>> iounmap(virt_addr); >>> - pageno = (phys_addr - mem->phys_base) >> page_shift; >>> + pageno = (phys_addr - mem->window.phys_base) >> page_shift; >>> size = ALIGN(size, mem->page_size); >>> order = pci_epc_mem_get_order(mem, size); >>> bitmap_release_region(mem->bitmap, pageno, order); >>> + mem->window.map_size -= size; >>> } >>> EXPORT_SYMBOL_GPL(pci_epc_mem_free_addr); >>> >>> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h >>> index f641bad..bee6f65 100644 >>> --- a/include/linux/pci-epc.h >>> +++ b/include/linux/pci-epc.h >>> @@ -48,7 +48,8 @@ struct pci_epc_ops { >>> void (*clear_bar)(struct pci_epc *epc, u8 func_no, >>> struct pci_epf_bar *epf_bar); >>> int (*map_addr)(struct pci_epc *epc, u8 func_no, >>> - phys_addr_t addr, u64 pci_addr, size_t size); >>> + phys_addr_t addr, int window, >>> + u64 pci_addr, size_t size); >>> void (*unmap_addr)(struct pci_epc *epc, u8 func_no, >>> phys_addr_t addr); >>> int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts); >>> @@ -64,17 +65,57 @@ struct pci_epc_ops { >>> struct module *owner; >>> }; >>> >>> +#define PCI_EPC_DEFAULT_WINDOW 0 >>> + >>> +/** >>> + * enum pci_epc_window_flags - flags info for pci_epc_mem_window >>> + * >>> + * This enum defines how the endpoint controller window should be used >>> + * for allocations. >>> + * >>> + * @PCI_EPC_WINDOW_FLAG_MULTI_ALLOC: Indicates multiple chunks of memory can be >>> + * allocated from same window >>> + * @PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC: Indicates only single memory allocation >>> + * is possible on the window >> >> Instead of NON_MULTI_ALLOC, we could simply have different page_size for >> different windows. For a platform that doesn't allow multiple alloc, >> page size will be equal to the window size. >> > I would still prefer this flag and not go with page size = window size > as we could allocate unnecessary memory Nor sure I understand you here. If you have PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC, wouldn't it mean, you cannot have more than 1 allocation in the entire window. Setting page size same as window size will also mean the same thing. > that might not be used and also the window sizes might be too large. IMHO We could still have flags to provide a type for a window and directing the allocation to a particular window with a type. But at-least for the use case that you are trying to solve, it's simpler to have page_size = window_size and the allocation algorithm need not change. Thanks Kishon ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 2/6] pci: endpoint: add support to handle features of outbound memory 2020-01-02 9:44 ` Kishon Vijay Abraham I @ 2020-01-02 9:59 ` Lad, Prabhakar 0 siblings, 0 replies; 27+ messages in thread From: Lad, Prabhakar @ 2020-01-02 9:59 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Bjorn Helgaas, Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Marek Vasut, Yoshihiro Shimoda, linux-pci, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML, LAK, Linux-Renesas, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, open list:ARM/Rockchip SoC..., Lad, Prabhakar Hi Kishon, On Thu, Jan 2, 2020 at 9:43 AM Kishon Vijay Abraham I <kishon@ti.com> wrote: > > Hi Prabhakar, > > On 18/12/19 10:53 PM, Lad, Prabhakar wrote: > > Hi Kishon, > > > > On Mon, Dec 16, 2019 at 11:34 AM Kishon Vijay Abraham I <kishon@ti.com> wrote: > >> > >> Hi Prabhakar, > >> > >> On 13/12/19 2:17 pm, wrote: > >>> From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > >>> > >>> rcar pcie controller has support to map multiple memory regions > >>> for mapping the outbound memory in local system, this feature > >>> inspires to add support for handling such features in endpoint > >>> framework. similar features exists on other controllers where > >>> outbound regions can be specifically used for low/high priority > >>> transactions, and regions can be flagged and used for allocation > >>> of large/small memory allocations. > >>> This patch adds support to handle such features, where the > >>> properties described for outbound regions are used whenever a > >>> request to memory is made. > >>> > >>> Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > >>> --- > >>> drivers/pci/controller/dwc/pcie-designware-ep.c | 30 ++-- > >>> drivers/pci/controller/pcie-cadence-ep.c | 11 +- > >>> drivers/pci/controller/pcie-rockchip-ep.c | 13 +- > >>> drivers/pci/endpoint/functions/pci-epf-test.c | 47 ++++-- > >>> drivers/pci/endpoint/pci-epc-core.c | 7 +- > >>> drivers/pci/endpoint/pci-epc-mem.c | 216 +++++++++++++++++++----- > >>> include/linux/pci-epc.h | 72 ++++++-- > >>> 7 files changed, 307 insertions(+), 89 deletions(-) > >>> > >>> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > >>> index 3dd2e26..be6aa94 100644 > >>> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > >>> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > >>> @@ -195,7 +195,7 @@ static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no, > >>> } > >>> > >>> static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, > >>> - phys_addr_t addr, > >>> + phys_addr_t addr, int window, > >>> u64 pci_addr, size_t size) > >>> { > >>> int ret; > >>> @@ -367,6 +367,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, > >>> unsigned int aligned_offset; > >>> u16 msg_ctrl, msg_data; > >>> u32 msg_addr_lower, msg_addr_upper, reg; > >>> + int window = PCI_EPC_DEFAULT_WINDOW; > >>> u64 msg_addr; > >>> bool has_upper; > >>> int ret; > >>> @@ -390,11 +391,11 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, > >>> reg = ep->msi_cap + PCI_MSI_DATA_32; > >>> msg_data = dw_pcie_readw_dbi(pci, reg); > >>> } > >>> - aligned_offset = msg_addr_lower & (epc->mem->page_size - 1); > >>> + aligned_offset = msg_addr_lower & (epc->mem[window]->page_size - 1); > >>> msg_addr = ((u64)msg_addr_upper) << 32 | > >>> (msg_addr_lower & ~aligned_offset); > >>> - ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, > >>> - epc->mem->page_size); > >>> + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, window, > >>> + msg_addr, epc->mem[window]->page_size); > >>> if (ret) > >>> return ret; > >>> > >>> @@ -416,6 +417,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > >>> u32 reg, msg_data, vec_ctrl; > >>> u64 tbl_addr, msg_addr, reg_u64; > >>> void __iomem *msix_tbl; > >>> + int window = PCI_EPC_DEFAULT_WINDOW; > >>> int ret; > >>> > >>> reg = ep->msix_cap + PCI_MSIX_TABLE; > >>> @@ -452,8 +454,8 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > >>> return -EPERM; > >>> } > >>> > >>> - ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, > >>> - epc->mem->page_size); > >>> + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, window, > >>> + msg_addr, epc->mem[window]->page_size); > >>> if (ret) > >>> return ret; > >>> > >>> @@ -466,10 +468,11 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > >>> > >>> void dw_pcie_ep_exit(struct dw_pcie_ep *ep) > >>> { > >>> + int window = PCI_EPC_DEFAULT_WINDOW; > >>> struct pci_epc *epc = ep->epc; > >>> > >>> pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, > >>> - epc->mem->page_size); > >>> + epc->mem[window]->page_size); > >>> > >>> pci_epc_mem_exit(epc); > >>> } > >>> @@ -499,9 +502,12 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > >>> u32 reg; > >>> void *addr; > >>> u8 hdr_type; > >>> + int window; > >>> unsigned int nbars; > >>> unsigned int offset; > >>> struct pci_epc *epc; > >>> + size_t msi_page_size; > >>> + struct pci_epc_mem_window mem_window; > >>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > >>> struct device *dev = pci->dev; > >>> struct device_node *np = dev->of_node; > >>> @@ -574,15 +580,17 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > >>> if (ret < 0) > >>> epc->max_functions = 1; > >>> > >>> - ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, > >>> - ep->page_size); > >>> + mem_window.phys_base = ep->phys_base; > >>> + mem_window.size = ep->addr_size; > >>> + ret = __pci_epc_mem_init(epc, &mem_window, 1, ep->page_size); > >>> if (ret < 0) { > >>> dev_err(dev, "Failed to initialize address space\n"); > >>> return ret; > >>> } > >>> > >>> - ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, > >>> - epc->mem->page_size); > >>> + msi_page_size = epc->mem[PCI_EPC_DEFAULT_WINDOW]->page_size; > >>> + ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, &window, > >>> + msi_page_size, 0x0); > >>> if (!ep->msi_mem) { > >>> dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); > >>> return -ENOMEM; > >>> diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c > >>> index def7820..2410706 100644 > >>> --- a/drivers/pci/controller/pcie-cadence-ep.c > >>> +++ b/drivers/pci/controller/pcie-cadence-ep.c > >>> @@ -172,7 +172,7 @@ static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, > >>> } > >>> > >>> static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr, > >>> - u64 pci_addr, size_t size) > >>> + int window, u64 pci_addr, size_t size) > >>> { > >>> struct cdns_pcie_ep *ep = epc_get_drvdata(epc); > >>> struct cdns_pcie *pcie = &ep->pcie; > >>> @@ -434,12 +434,14 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) > >>> { > >>> struct device *dev = &pdev->dev; > >>> struct device_node *np = dev->of_node; > >>> + struct pci_epc_mem_window mem_window; > >>> struct cdns_pcie_ep *ep; > >>> struct cdns_pcie *pcie; > >>> struct pci_epc *epc; > >>> struct resource *res; > >>> int ret; > >>> int phy_count; > >>> + int window; > >>> > >>> ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); > >>> if (!ep) > >>> @@ -502,15 +504,16 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) > >>> if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) > >>> epc->max_functions = 1; > >>> > >>> - ret = pci_epc_mem_init(epc, pcie->mem_res->start, > >>> - resource_size(pcie->mem_res)); > >>> + mem_window.phys_base = pcie->mem_res->start; > >>> + mem_window.size = resource_size(pcie->mem_res); > >>> + ret = pci_epc_mem_init(epc, &mem_window, 1); > >>> if (ret < 0) { > >>> dev_err(dev, "failed to initialize the memory space\n"); > >>> goto err_init; > >>> } > >>> > >>> ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, > >>> - SZ_128K); > >>> + &window, SZ_128K, 0x0); > >>> if (!ep->irq_cpu_addr) { > >>> dev_err(dev, "failed to reserve memory space for MSI\n"); > >>> ret = -ENOMEM; > >>> diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c > >>> index d743b0a..828052c 100644 > >>> --- a/drivers/pci/controller/pcie-rockchip-ep.c > >>> +++ b/drivers/pci/controller/pcie-rockchip-ep.c > >>> @@ -256,8 +256,8 @@ static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, > >>> } > >>> > >>> static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, > >>> - phys_addr_t addr, u64 pci_addr, > >>> - size_t size) > >>> + phys_addr_t addr, int window, > >>> + u64 pci_addr, size_t size) > >>> { > >>> struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > >>> struct rockchip_pcie *pcie = &ep->rockchip; > >>> @@ -562,11 +562,13 @@ static const struct of_device_id rockchip_pcie_ep_of_match[] = { > >>> > >>> static int rockchip_pcie_ep_probe(struct platform_device *pdev) > >>> { > >>> + struct pci_epc_mem_window mem_window; > >>> struct device *dev = &pdev->dev; > >>> struct rockchip_pcie_ep *ep; > >>> struct rockchip_pcie *rockchip; > >>> struct pci_epc *epc; > >>> size_t max_regions; > >>> + int window; > >>> int err; > >>> > >>> ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); > >>> @@ -614,15 +616,16 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) > >>> /* Only enable function 0 by default */ > >>> rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); > >>> > >>> - err = pci_epc_mem_init(epc, rockchip->mem_res->start, > >>> - resource_size(rockchip->mem_res)); > >>> + mem_window.phys_base = rockchip->mem_res->start; > >>> + mem_window.size = resource_size(rockchip->mem_res); > >>> + err = pci_epc_mem_init(epc, &mem_window, 1); > >>> if (err < 0) { > >>> dev_err(dev, "failed to initialize the memory space\n"); > >>> goto err_uninit_port; > >>> } > >>> > >>> ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, > >>> - SZ_128K); > >>> + &window, SZ_128K, 0x0); > >>> if (!ep->irq_cpu_addr) { > >>> dev_err(dev, "failed to reserve memory space for MSI\n"); > >>> err = -ENOMEM; > >>> diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c > >>> index 1cfe368..4768d54 100644 > >>> --- a/drivers/pci/endpoint/functions/pci-epf-test.c > >>> +++ b/drivers/pci/endpoint/functions/pci-epf-test.c > >>> @@ -84,8 +84,14 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) > >>> struct pci_epc *epc = epf->epc; > >>> enum pci_barno test_reg_bar = epf_test->test_reg_bar; > >>> struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; > >>> - > >>> - src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size); > >>> + int window; > >>> + > >>> + src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, > >>> + &window, reg->size, > >>> + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | > >>> + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | > >>> + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | > >>> + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); > >>> if (!src_addr) { > >>> dev_err(dev, "Failed to allocate source address\n"); > >>> reg->status = STATUS_SRC_ADDR_INVALID; > >>> @@ -93,15 +99,20 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) > >>> goto err; > >>> } > >>> > >>> - ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, reg->src_addr, > >>> - reg->size); > >>> + ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, window, > >>> + reg->src_addr, reg->size); > >>> if (ret) { > >>> dev_err(dev, "Failed to map source address\n"); > >>> reg->status = STATUS_SRC_ADDR_INVALID; > >>> goto err_src_addr; > >>> } > >>> > >>> - dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size); > >>> + dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, > >>> + &window, reg->size, > >>> + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | > >>> + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | > >>> + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | > >>> + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); > >>> if (!dst_addr) { > >>> dev_err(dev, "Failed to allocate destination address\n"); > >>> reg->status = STATUS_DST_ADDR_INVALID; > >>> @@ -109,8 +120,8 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test) > >>> goto err_src_map_addr; > >>> } > >>> > >>> - ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, reg->dst_addr, > >>> - reg->size); > >>> + ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, window, > >>> + reg->dst_addr, reg->size); > >>> if (ret) { > >>> dev_err(dev, "Failed to map destination address\n"); > >>> reg->status = STATUS_DST_ADDR_INVALID; > >>> @@ -146,8 +157,13 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test) > >>> struct pci_epc *epc = epf->epc; > >>> enum pci_barno test_reg_bar = epf_test->test_reg_bar; > >>> struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; > >>> + int window; > >>> > >>> - src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); > >>> + src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, &window, reg->size, > >>> + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | > >>> + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | > >>> + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | > >>> + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); > >>> if (!src_addr) { > >>> dev_err(dev, "Failed to allocate address\n"); > >>> reg->status = STATUS_SRC_ADDR_INVALID; > >>> @@ -155,8 +171,8 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test) > >>> goto err; > >>> } > >>> > >>> - ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->src_addr, > >>> - reg->size); > >>> + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, window, > >>> + reg->src_addr, reg->size); > >>> if (ret) { > >>> dev_err(dev, "Failed to map address\n"); > >>> reg->status = STATUS_SRC_ADDR_INVALID; > >>> @@ -193,13 +209,18 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test) > >>> void __iomem *dst_addr; > >>> void *buf; > >>> phys_addr_t phys_addr; > >>> + int window; > >>> struct pci_epf *epf = epf_test->epf; > >>> struct device *dev = &epf->dev; > >>> struct pci_epc *epc = epf->epc; > >>> enum pci_barno test_reg_bar = epf_test->test_reg_bar; > >>> struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; > >>> > >>> - dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); > >>> + dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, &window, reg->size, > >>> + PCI_EPC_WINDOW_FLAG_LARGE_ALLOC | > >>> + PCI_EPC_WINDOW_FLAG_SMALL_ALLOC | > >>> + PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC | > >>> + PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC); > >>> if (!dst_addr) { > >>> dev_err(dev, "Failed to allocate address\n"); > >>> reg->status = STATUS_DST_ADDR_INVALID; > >>> @@ -207,8 +228,8 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test) > >>> goto err; > >>> } > >>> > >>> - ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->dst_addr, > >>> - reg->size); > >>> + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, window, > >>> + reg->dst_addr, reg->size); > >>> if (ret) { > >>> dev_err(dev, "Failed to map address\n"); > >>> reg->status = STATUS_DST_ADDR_INVALID; > >>> diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c > >>> index 2091508..289c266 100644 > >>> --- a/drivers/pci/endpoint/pci-epc-core.c > >>> +++ b/drivers/pci/endpoint/pci-epc-core.c > >>> @@ -358,13 +358,15 @@ EXPORT_SYMBOL_GPL(pci_epc_unmap_addr); > >>> * @epc: the EPC device on which address is allocated > >>> * @func_no: the endpoint function number in the EPC device > >>> * @phys_addr: physical address of the local system > >>> + * @window: index to the window region where PCI address will be mapped > >>> * @pci_addr: PCI address to which the physical address should be mapped > >>> * @size: the size of the allocation > >>> * > >>> * Invoke to map CPU address with PCI address. > >>> */ > >>> int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, > >>> - phys_addr_t phys_addr, u64 pci_addr, size_t size) > >>> + phys_addr_t phys_addr, int window, > >>> + u64 pci_addr, size_t size) > >>> { > >>> int ret; > >>> unsigned long flags; > >>> @@ -376,7 +378,8 @@ int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, > >>> return 0; > >>> > >>> spin_lock_irqsave(&epc->lock, flags); > >>> - ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size); > >>> + ret = epc->ops->map_addr(epc, func_no, phys_addr, > >>> + window, pci_addr, size); > >>> spin_unlock_irqrestore(&epc->lock, flags); > >>> > >>> return ret; > >>> diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c > >>> index 2bf8bd1..4b610cd 100644 > >>> --- a/drivers/pci/endpoint/pci-epc-mem.c > >>> +++ b/drivers/pci/endpoint/pci-epc-mem.c > >>> @@ -39,56 +39,78 @@ static int pci_epc_mem_get_order(struct pci_epc_mem *mem, size_t size) > >>> * __pci_epc_mem_init() - initialize the pci_epc_mem structure > >>> * @epc: the EPC device that invoked pci_epc_mem_init > >>> * @phys_base: the physical address of the base > >>> - * @size: the size of the address space > >>> + * @num_windows: number of windows device supports > >>> * @page_size: size of each page > >>> * > >>> * Invoke to initialize the pci_epc_mem structure used by the > >>> * endpoint functions to allocate mapped PCI address. > >>> */ > >>> -int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_base, size_t size, > >>> - size_t page_size) > >>> +int __pci_epc_mem_init(struct pci_epc *epc, struct pci_epc_mem_window *windows, > >>> + int num_windows, size_t page_size) > >>> { > >>> - int ret; > >>> - struct pci_epc_mem *mem; > >>> - unsigned long *bitmap; > >>> + struct pci_epc_mem *mem = NULL; > >>> + unsigned long *bitmap = NULL; > >>> unsigned int page_shift; > >>> - int pages; > >>> int bitmap_size; > >>> + int pages; > >>> + int ret; > >>> + int i; > >>> + > >>> + epc->mem_windows = 0; > >>> + > >>> + if (!windows) > >>> + return -EINVAL; > >>> + > >>> + if (num_windows <= 0) > >>> + return -EINVAL; > >>> > >>> if (page_size < PAGE_SIZE) > >>> page_size = PAGE_SIZE; > >>> > >>> page_shift = ilog2(page_size); > >>> - pages = size >> page_shift; > >>> - bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); > >>> > >>> - mem = kzalloc(sizeof(*mem), GFP_KERNEL); > >>> - if (!mem) { > >>> - ret = -ENOMEM; > >>> - goto err; > >>> - } > >>> + epc->mem = kcalloc(num_windows, sizeof(*mem), GFP_KERNEL); > >>> + if (!epc->mem) > >>> + return -EINVAL; > >>> > >>> - bitmap = kzalloc(bitmap_size, GFP_KERNEL); > >>> - if (!bitmap) { > >>> - ret = -ENOMEM; > >>> - goto err_mem; > >>> - } > >>> + for (i = 0; i < num_windows; i++) { > >>> + pages = windows[i].phys_base >> page_shift; > >>> + bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); > >>> > >>> - mem->bitmap = bitmap; > >>> - mem->phys_base = phys_base; > >>> - mem->page_size = page_size; > >>> - mem->pages = pages; > >>> - mem->size = size; > >>> + mem = kzalloc(sizeof(*mem), GFP_KERNEL); > >>> + if (!mem) { > >>> + ret = -ENOMEM; > >>> + goto err_mem; > >>> + } > >>> > >>> - epc->mem = mem; > >>> + bitmap = kzalloc(bitmap_size, GFP_KERNEL); > >>> + if (!bitmap) { > >>> + ret = -ENOMEM; > >>> + goto err_mem; > >>> + } > >>> + > >>> + mem->bitmap = bitmap; > >>> + mem->window.phys_base = windows[i].phys_base; > >>> + mem->page_size = page_size; > >>> + mem->pages = pages; > >>> + mem->window.size = windows[i].size; > >>> + mem->window.map_size = 0; > >>> + mem->window.flags = windows[i].flags; > >>> + > >>> + epc->mem[i] = mem; > >>> + } > >>> + epc->mem_windows = num_windows; > >>> > >>> return 0; > >>> > >>> err_mem: > >>> - kfree(mem); > >>> + for (; i >= 0; i--) { > >>> + kfree(mem->bitmap); > >>> + kfree(epc->mem[i]); > >>> + } > >>> + kfree(epc->mem); > >>> > >>> -err: > >>> -return ret; > >>> + return ret; > >>> } > >>> EXPORT_SYMBOL_GPL(__pci_epc_mem_init); > >>> > >>> @@ -101,48 +123,152 @@ EXPORT_SYMBOL_GPL(__pci_epc_mem_init); > >>> */ > >>> void pci_epc_mem_exit(struct pci_epc *epc) > >>> { > >>> - struct pci_epc_mem *mem = epc->mem; > >>> + struct pci_epc_mem *mem; > >>> + int i; > >>> + > >>> + if (!epc->mem_windows) > >>> + return; > >>> + > >>> + for (i = 0; i <= epc->mem_windows; i--) { > >>> + mem = epc->mem[i]; > >>> + kfree(mem->bitmap); > >>> + kfree(epc->mem[i]); > >>> + } > >>> + kfree(epc->mem); > >>> > >>> epc->mem = NULL; > >>> - kfree(mem->bitmap); > >>> - kfree(mem); > >>> + epc->mem_windows = 0; > >>> } > >>> EXPORT_SYMBOL_GPL(pci_epc_mem_exit); > >>> > >>> +static int pci_epc_find_best_fit_window(struct pci_epc *epc, size_t size, > >>> + u32 flags) > >>> +{ > >>> + size_t window_least_size = 0; > >>> + int best_fit_window = -1; > >>> + struct pci_epc_mem *mem; > >>> + size_t actual_size; > >>> + size_t avail_size; > >>> + u32 win_flags; > >>> + int i; > >>> + > >>> + for (i = 0; i < epc->mem_windows; i++) { > >>> + mem = epc->mem[i]; > >>> + win_flags = mem->window.flags; > >>> + > >>> + actual_size = ALIGN(size, mem->page_size); > >>> + avail_size = mem->window.size - mem->window.map_size; > >>> + > >>> + if (win_flags == 0x0) { > >>> + if (best_fit_window == -1) { > >>> + if (actual_size <= avail_size) { > >>> + best_fit_window = i; > >>> + window_least_size = mem->window.size; > >>> + } > >>> + } else { > >>> + if (actual_size <= avail_size && > >>> + mem->window.size < window_least_size) { > >>> + best_fit_window = i; > >>> + window_least_size = mem->window.size; > >>> + } > >>> + } > >>> + } else { > >>> + if (mem->window.map_size && > >>> + (win_flags | PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC)) > >>> + continue; > >>> + > >>> + if (!(win_flags | flags)) > >>> + continue; > >>> + > >>> + if (best_fit_window == -1) { > >>> + if (actual_size <= avail_size) { > >>> + best_fit_window = i; > >>> + window_least_size = mem->window.size; > >>> + } > >>> + } else { > >>> + if (actual_size <= avail_size && > >>> + mem->window.size < window_least_size) { > >>> + best_fit_window = i; > >>> + window_least_size = mem->window.size; > >>> + } > >>> + } > >>> + } > >>> + } > >>> + > >>> + return best_fit_window; > >>> +} > >>> + > >>> /** > >>> * pci_epc_mem_alloc_addr() - allocate memory address from EPC addr space > >>> * @epc: the EPC device on which memory has to be allocated > >>> * @phys_addr: populate the allocated physical address here > >>> + * @window: populate the window here which will be used to map PCI address > >>> * @size: the size of the address space that has to be allocated > >>> + * @flags: look for window as requested in flags > >>> * > >>> * Invoke to allocate memory address from the EPC address space. This > >>> * is usually done to map the remote RC address into the local system. > >>> */ > >>> void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, > >>> - phys_addr_t *phys_addr, size_t size) > >>> + phys_addr_t *phys_addr, > >>> + int *window, size_t size, uint32_t flags) > >>> { > >>> + int best_fit = PCI_EPC_DEFAULT_WINDOW; > >>> + void __iomem *virt_addr = NULL; > >>> + struct pci_epc_mem *mem; > >>> + unsigned int page_shift; > >>> int pageno; > >>> - void __iomem *virt_addr; > >>> - struct pci_epc_mem *mem = epc->mem; > >>> - unsigned int page_shift = ilog2(mem->page_size); > >>> int order; > >>> > >>> + if (epc->mem_windows <= 0) > >>> + return NULL; > >>> + > >>> + if (epc->mem_windows > 1) { > >>> + best_fit = pci_epc_find_best_fit_window(epc, size, flags); > >>> + if (best_fit < 0) > >>> + return NULL; > >>> + } > >>> + > >>> + mem = epc->mem[best_fit]; > >>> size = ALIGN(size, mem->page_size); > >>> + if (size > (mem->window.size - mem->window.map_size)) > >>> + return NULL; > >>> + page_shift = ilog2(mem->page_size); > >>> order = pci_epc_mem_get_order(mem, size); > >>> > >>> pageno = bitmap_find_free_region(mem->bitmap, mem->pages, order); > >>> if (pageno < 0) > >>> return NULL; > >>> > >>> - *phys_addr = mem->phys_base + (pageno << page_shift); > >>> + *phys_addr = mem->window.phys_base + (pageno << page_shift); > >>> virt_addr = ioremap(*phys_addr, size); > >>> - if (!virt_addr) > >>> + if (!virt_addr) { > >>> bitmap_release_region(mem->bitmap, pageno, order); > >>> + } else { > >>> + mem->window.map_size += size; > >>> + *window = best_fit; > >>> + } > >>> > >>> return virt_addr; > >>> } > >>> EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); > >>> > >>> +static int pci_epc_get_matching_window(struct pci_epc *epc, > >>> + phys_addr_t phys_addr) > >>> +{ > >>> + struct pci_epc_mem *mem; > >>> + int i; > >>> + > >>> + for (i = 0; i < epc->mem_windows; i++) { > >>> + mem = epc->mem[i]; > >>> + > >>> + if (mem->window.phys_base == phys_addr) > >>> + return i; > >>> + } > >>> + > >>> + return -EINVAL; > >>> +} > >>> + > >>> /** > >>> * pci_epc_mem_free_addr() - free the allocated memory address > >>> * @epc: the EPC device on which memory was allocated > >>> @@ -155,16 +281,26 @@ EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); > >>> void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr, > >>> void __iomem *virt_addr, size_t size) > >>> { > >>> + struct pci_epc_mem *mem; > >>> + unsigned int page_shift; > >>> + int window = 0; > >>> int pageno; > >>> - struct pci_epc_mem *mem = epc->mem; > >>> - unsigned int page_shift = ilog2(mem->page_size); > >>> int order; > >>> > >>> + if (epc->mem_windows > 1) { > >>> + window = pci_epc_get_matching_window(epc, phys_addr); > >>> + if (window < 0) > >>> + return; > >>> + } > >>> + > >>> + mem = epc->mem[window]; > >>> + page_shift = ilog2(mem->page_size); > >>> iounmap(virt_addr); > >>> - pageno = (phys_addr - mem->phys_base) >> page_shift; > >>> + pageno = (phys_addr - mem->window.phys_base) >> page_shift; > >>> size = ALIGN(size, mem->page_size); > >>> order = pci_epc_mem_get_order(mem, size); > >>> bitmap_release_region(mem->bitmap, pageno, order); > >>> + mem->window.map_size -= size; > >>> } > >>> EXPORT_SYMBOL_GPL(pci_epc_mem_free_addr); > >>> > >>> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h > >>> index f641bad..bee6f65 100644 > >>> --- a/include/linux/pci-epc.h > >>> +++ b/include/linux/pci-epc.h > >>> @@ -48,7 +48,8 @@ struct pci_epc_ops { > >>> void (*clear_bar)(struct pci_epc *epc, u8 func_no, > >>> struct pci_epf_bar *epf_bar); > >>> int (*map_addr)(struct pci_epc *epc, u8 func_no, > >>> - phys_addr_t addr, u64 pci_addr, size_t size); > >>> + phys_addr_t addr, int window, > >>> + u64 pci_addr, size_t size); > >>> void (*unmap_addr)(struct pci_epc *epc, u8 func_no, > >>> phys_addr_t addr); > >>> int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts); > >>> @@ -64,17 +65,57 @@ struct pci_epc_ops { > >>> struct module *owner; > >>> }; > >>> > >>> +#define PCI_EPC_DEFAULT_WINDOW 0 > >>> + > >>> +/** > >>> + * enum pci_epc_window_flags - flags info for pci_epc_mem_window > >>> + * > >>> + * This enum defines how the endpoint controller window should be used > >>> + * for allocations. > >>> + * > >>> + * @PCI_EPC_WINDOW_FLAG_MULTI_ALLOC: Indicates multiple chunks of memory can be > >>> + * allocated from same window > >>> + * @PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC: Indicates only single memory allocation > >>> + * is possible on the window > >> > >> Instead of NON_MULTI_ALLOC, we could simply have different page_size for > >> different windows. For a platform that doesn't allow multiple alloc, > >> page size will be equal to the window size. > >> > > I would still prefer this flag and not go with page size = window size > > as we could allocate unnecessary memory > > Nor sure I understand you here. If you have > PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC, wouldn't it mean, you cannot have > more than 1 allocation in the entire window. Setting page size same as > window size will also mean the same thing. > > that might not be used and also the window sizes might be too large. > > IMHO We could still have flags to provide a type for a window and > directing the allocation to a particular window with a type. But > at-least for the use case that you are trying to solve, it's simpler to > have page_size = window_size and the allocation algorithm need not change. > this will make things simpler, I'll drop all the above flags and OF code to parse the regions, and go with just setting page-size = window-size for my use case. Cheers, --Prabhakar ^ permalink raw reply [flat|nested] 27+ messages in thread
* [v2 3/6] of: address: add support to parse PCI outbound-ranges 2019-12-13 8:47 [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs Lad Prabhakar 2019-12-13 8:47 ` [v2 1/6] pci: pcie-rcar: preparation for adding endpoint support Lad Prabhakar 2019-12-13 8:47 ` [v2 2/6] pci: endpoint: add support to handle features of outbound memory Lad Prabhakar @ 2019-12-13 8:47 ` Lad Prabhakar 2019-12-13 15:07 ` Rob Herring 2019-12-13 21:05 ` Bjorn Helgaas 2019-12-13 8:47 ` [v2 4/6] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller Lad Prabhakar ` (3 subsequent siblings) 6 siblings, 2 replies; 27+ messages in thread From: Lad Prabhakar @ 2019-12-13 8:47 UTC (permalink / raw) To: Bjorn Helgaas, Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci Cc: Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel, linux-arm-kernel, linux-renesas-soc, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> this patch adds support to parse PCI outbound-ranges, the outbound-regions are similar to pci ranges except it doesn't have pci address, below is the format for bar-ranges: outbound-ranges = <flags upper32_cpuaddr lower32_cpuaddr upper32_size lower32_size>; Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/of/address.c | 44 ++++++++++++++++++++++++++++++++++++++++---- include/linux/of_address.h | 21 +++++++++++++++++++++ 2 files changed, 61 insertions(+), 4 deletions(-) diff --git a/drivers/of/address.c b/drivers/of/address.c index 978427a..ca4643c 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -233,9 +233,9 @@ int of_pci_address_to_resource(struct device_node *dev, int bar, EXPORT_SYMBOL_GPL(of_pci_address_to_resource); static int parser_init(struct of_pci_range_parser *parser, - struct device_node *node, const char *name) + struct device_node *node, const char *name, + const int na, const int ns) { - const int na = 3, ns = 2; int rlen; parser->node = node; @@ -254,17 +254,30 @@ static int parser_init(struct of_pci_range_parser *parser, int of_pci_range_parser_init(struct of_pci_range_parser *parser, struct device_node *node) { - return parser_init(parser, node, "ranges"); + const int na = 3, ns = 2; + + return parser_init(parser, node, "ranges", na, ns); } EXPORT_SYMBOL_GPL(of_pci_range_parser_init); int of_pci_dma_range_parser_init(struct of_pci_range_parser *parser, struct device_node *node) { - return parser_init(parser, node, "dma-ranges"); + const int na = 3, ns = 2; + + return parser_init(parser, node, "dma-ranges", na, ns); } EXPORT_SYMBOL_GPL(of_pci_dma_range_parser_init); +int of_pci_outbound_range_parser_init(struct of_pci_range_parser *parser, + struct device_node *node) +{ + const int na = 1, ns = 2; + + return parser_init(parser, node, "outbound-ranges", na, ns); +} +EXPORT_SYMBOL_GPL(of_pci_outbound_range_parser_init); + struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, struct of_pci_range *range) { @@ -310,6 +323,29 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, } EXPORT_SYMBOL_GPL(of_pci_range_parser_one); +struct of_pci_outbound_range +*of_pci_outbound_range_parser_one(struct of_pci_range_parser *parser, + struct of_pci_outbound_range *range) +{ + const int na = 1, ns = 2; + + if (!range) + return NULL; + + if (!parser->range || parser->range + parser->np > parser->end) + return NULL; + + range->flags = be32_to_cpup(parser->range); + range->cpu_addr = of_translate_address(parser->node, + parser->range + na); + range->size = of_read_number(parser->range + parser->pna + na, ns); + + parser->range += parser->np; + + return range; +} +EXPORT_SYMBOL_GPL(of_pci_outbound_range_parser_one); + /* * of_pci_range_to_resource - Create a resource from an of_pci_range * @range: the PCI range that describes the resource diff --git a/include/linux/of_address.h b/include/linux/of_address.h index 30e40fb..93b3be3 100644 --- a/include/linux/of_address.h +++ b/include/linux/of_address.h @@ -22,9 +22,18 @@ struct of_pci_range { u32 flags; }; +struct of_pci_outbound_range { + u32 flags; + u64 cpu_addr; + u64 size; +}; + #define for_each_of_pci_range(parser, range) \ for (; of_pci_range_parser_one(parser, range);) +#define for_each_of_pci_outbound_range(parser, range) \ + for (; of_pci_outbound_range_parser_one(parser, range);) + /* Translate a DMA address from device space to CPU space */ extern u64 of_translate_dma_address(struct device_node *dev, const __be32 *in_addr); @@ -52,9 +61,14 @@ extern int of_pci_range_parser_init(struct of_pci_range_parser *parser, struct device_node *node); extern int of_pci_dma_range_parser_init(struct of_pci_range_parser *parser, struct device_node *node); +extern int of_pci_outbound_range_parser_init(struct of_pci_range_parser *parser, + struct device_node *node); extern struct of_pci_range *of_pci_range_parser_one( struct of_pci_range_parser *parser, struct of_pci_range *range); +extern struct of_pci_outbound_range +*of_pci_outbound_range_parser_one(struct of_pci_range_parser *parser, + struct of_pci_outbound_range *range); extern int of_dma_get_range(struct device_node *np, u64 *dma_addr, u64 *paddr, u64 *size); extern bool of_dma_is_coherent(struct device_node *np); @@ -97,6 +111,13 @@ static inline int of_pci_dma_range_parser_init(struct of_pci_range_parser *parse return -ENOSYS; } +static inline int +of_pci_outbound_range_parser_init(struct of_pci_range_parser *parser, + struct device_node *node) +{ + return -ENOSYS; +} + static inline struct of_pci_range *of_pci_range_parser_one( struct of_pci_range_parser *parser, struct of_pci_range *range) -- 2.7.4 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [v2 3/6] of: address: add support to parse PCI outbound-ranges 2019-12-13 8:47 ` [v2 3/6] of: address: add support to parse PCI outbound-ranges Lad Prabhakar @ 2019-12-13 15:07 ` Rob Herring 2019-12-16 8:49 ` Lad, Prabhakar 2019-12-13 21:05 ` Bjorn Helgaas 1 sibling, 1 reply; 27+ messages in thread From: Rob Herring @ 2019-12-13 15:07 UTC (permalink / raw) To: Lad Prabhakar Cc: Bjorn Helgaas, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, PCI, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list:MEDIA DRIVERS FOR RENESAS - FCP, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, open list:ARM/Rockchip SoC..., Lad, Prabhakar On Fri, Dec 13, 2019 at 2:48 AM Lad Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > this patch adds support to parse PCI outbound-ranges, the > outbound-regions are similar to pci ranges except it doesn't > have pci address, below is the format for bar-ranges: > > outbound-ranges = <flags upper32_cpuaddr lower32_cpuaddr > upper32_size lower32_size>; You can't just make up a new ranges property. Especially one that doesn't follow how 'ranges' works. We already have 'dma-ranges' to translate device to memory addresses. Explain the problem or feature you need, not the solution you came up with. Why do you need this and other endpoint bindings haven't? Rob ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 3/6] of: address: add support to parse PCI outbound-ranges 2019-12-13 15:07 ` Rob Herring @ 2019-12-16 8:49 ` Lad, Prabhakar 2019-12-19 23:31 ` Rob Herring 0 siblings, 1 reply; 27+ messages in thread From: Lad, Prabhakar @ 2019-12-16 8:49 UTC (permalink / raw) To: Rob Herring Cc: Bjorn Helgaas, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, PCI, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list:MEDIA DRIVERS FOR RENESAS - FCP, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, open list:ARM/Rockchip SoC..., Lad, Prabhakar Hi Rob, Thank you for the review. On Fri, Dec 13, 2019 at 8:37 PM Rob Herring <robh+dt@kernel.org> wrote: > > On Fri, Dec 13, 2019 at 2:48 AM Lad Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > > > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > this patch adds support to parse PCI outbound-ranges, the > > outbound-regions are similar to pci ranges except it doesn't > > have pci address, below is the format for bar-ranges: > > > > outbound-ranges = <flags upper32_cpuaddr lower32_cpuaddr > > upper32_size lower32_size>; > > You can't just make up a new ranges property. Especially one that > doesn't follow how 'ranges' works. We already have 'dma-ranges' to > translate device to memory addresses. > > Explain the problem or feature you need, not the solution you came up > with. Why do you need this and other endpoint bindings haven't? > rcar SoC's supports multiple outbound region for mapping the PCI address locally to the system. This lead to discussion where there exist controllers which support regions for high/low priority transfer and similarly regions for large/small memory allocations, as a result a new ranges property was added, where we can specify the flags which would indicate how the outbound region can be used during requests. The current endpoint controller drivers just support single region. Cheers, --Prabhakar ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 3/6] of: address: add support to parse PCI outbound-ranges 2019-12-16 8:49 ` Lad, Prabhakar @ 2019-12-19 23:31 ` Rob Herring 2020-01-02 8:44 ` Lad, Prabhakar 0 siblings, 1 reply; 27+ messages in thread From: Rob Herring @ 2019-12-19 23:31 UTC (permalink / raw) To: Lad, Prabhakar Cc: Bjorn Helgaas, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, PCI, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list:MEDIA DRIVERS FOR RENESAS - FCP, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, open list:ARM/Rockchip SoC..., Lad, Prabhakar On Mon, Dec 16, 2019 at 08:49:23AM +0000, Lad, Prabhakar wrote: > Hi Rob, > > Thank you for the review. > > On Fri, Dec 13, 2019 at 8:37 PM Rob Herring <robh+dt@kernel.org> wrote: > > > > On Fri, Dec 13, 2019 at 2:48 AM Lad Prabhakar > > <prabhakar.csengg@gmail.com> wrote: > > > > > > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > this patch adds support to parse PCI outbound-ranges, the > > > outbound-regions are similar to pci ranges except it doesn't > > > have pci address, below is the format for bar-ranges: > > > > > > outbound-ranges = <flags upper32_cpuaddr lower32_cpuaddr > > > upper32_size lower32_size>; > > > > You can't just make up a new ranges property. Especially one that > > doesn't follow how 'ranges' works. We already have 'dma-ranges' to > > translate device to memory addresses. > > > > Explain the problem or feature you need, not the solution you came up > > with. Why do you need this and other endpoint bindings haven't? > > > rcar SoC's supports multiple outbound region for mapping the PCI address > locally to the system. This lead to discussion where there exist controllers > which support regions for high/low priority transfer and similarly regions > for large/small memory allocations, as a result a new ranges property was > added, where we can specify the flags which would indicate how the outbound > region can be used during requests. What are the flags? Rob ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 3/6] of: address: add support to parse PCI outbound-ranges 2019-12-19 23:31 ` Rob Herring @ 2020-01-02 8:44 ` Lad, Prabhakar 2020-01-02 22:55 ` Rob Herring 0 siblings, 1 reply; 27+ messages in thread From: Lad, Prabhakar @ 2020-01-02 8:44 UTC (permalink / raw) To: Rob Herring Cc: Bjorn Helgaas, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, PCI, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list:MEDIA DRIVERS FOR RENESAS - FCP, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, open list:ARM/Rockchip SoC..., Lad, Prabhakar Hi Rob, On Thu, Dec 19, 2019 at 11:31 PM Rob Herring <robh@kernel.org> wrote: > > On Mon, Dec 16, 2019 at 08:49:23AM +0000, Lad, Prabhakar wrote: > > Hi Rob, > > > > Thank you for the review. > > > > On Fri, Dec 13, 2019 at 8:37 PM Rob Herring <robh+dt@kernel.org> wrote: > > > > > > On Fri, Dec 13, 2019 at 2:48 AM Lad Prabhakar > > > <prabhakar.csengg@gmail.com> wrote: > > > > > > > > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > this patch adds support to parse PCI outbound-ranges, the > > > > outbound-regions are similar to pci ranges except it doesn't > > > > have pci address, below is the format for bar-ranges: > > > > > > > > outbound-ranges = <flags upper32_cpuaddr lower32_cpuaddr > > > > upper32_size lower32_size>; > > > > > > You can't just make up a new ranges property. Especially one that > > > doesn't follow how 'ranges' works. We already have 'dma-ranges' to > > > translate device to memory addresses. > > > > > > Explain the problem or feature you need, not the solution you came up > > > with. Why do you need this and other endpoint bindings haven't? > > > > > rcar SoC's supports multiple outbound region for mapping the PCI address > > locally to the system. This lead to discussion where there exist controllers > > which support regions for high/low priority transfer and similarly regions > > for large/small memory allocations, as a result a new ranges property was > > added, where we can specify the flags which would indicate how the outbound > > region can be used during requests. > > What are the flags? below are the flags which were discussed in first version of the series, but since the driver is currently using just PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC flag I'll be dropping them in next version (suggested by Kishon) and rest will be added as and when required by the driver. * @PCI_EPC_WINDOW_FLAG_MULTI_ALLOC: Indicates multiple chunks of memory can be * allocated from same window * @PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC: Indicates only single memory allocation * is possible on the window * @PCI_EPC_WINDOW_FLAG_LARGE_ALLOC: Window is used for large memory allocation * @PCI_EPC_WINDOW_FLAG_SMALL_ALLOC: Window is used for small memory allocation * @PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC: Window is used for high priority data * transfers * @PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC: Window is used for low priority data * transfers Cheers, --Prabhakar ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 3/6] of: address: add support to parse PCI outbound-ranges 2020-01-02 8:44 ` Lad, Prabhakar @ 2020-01-02 22:55 ` Rob Herring 0 siblings, 0 replies; 27+ messages in thread From: Rob Herring @ 2020-01-02 22:55 UTC (permalink / raw) To: Lad, Prabhakar Cc: Bjorn Helgaas, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, PCI, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list:MEDIA DRIVERS FOR RENESAS - FCP, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, open list:ARM/Rockchip SoC..., Lad, Prabhakar On Thu, Jan 2, 2020 at 1:44 AM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > Hi Rob, > > On Thu, Dec 19, 2019 at 11:31 PM Rob Herring <robh@kernel.org> wrote: > > > > On Mon, Dec 16, 2019 at 08:49:23AM +0000, Lad, Prabhakar wrote: > > > Hi Rob, > > > > > > Thank you for the review. > > > > > > On Fri, Dec 13, 2019 at 8:37 PM Rob Herring <robh+dt@kernel.org> wrote: > > > > > > > > On Fri, Dec 13, 2019 at 2:48 AM Lad Prabhakar > > > > <prabhakar.csengg@gmail.com> wrote: > > > > > > > > > > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > this patch adds support to parse PCI outbound-ranges, the > > > > > outbound-regions are similar to pci ranges except it doesn't > > > > > have pci address, below is the format for bar-ranges: > > > > > > > > > > outbound-ranges = <flags upper32_cpuaddr lower32_cpuaddr > > > > > upper32_size lower32_size>; > > > > > > > > You can't just make up a new ranges property. Especially one that > > > > doesn't follow how 'ranges' works. We already have 'dma-ranges' to > > > > translate device to memory addresses. > > > > > > > > Explain the problem or feature you need, not the solution you came up > > > > with. Why do you need this and other endpoint bindings haven't? > > > > > > > rcar SoC's supports multiple outbound region for mapping the PCI address > > > locally to the system. This lead to discussion where there exist controllers > > > which support regions for high/low priority transfer and similarly regions > > > for large/small memory allocations, as a result a new ranges property was > > > added, where we can specify the flags which would indicate how the outbound > > > region can be used during requests. > > > > What are the flags? > > below are the flags which were discussed in first version of the > series, but since the driver is > currently using just PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC flag I'll be > dropping them in > next version (suggested by Kishon) and rest will be added as and when > required by the driver. > > * @PCI_EPC_WINDOW_FLAG_MULTI_ALLOC: Indicates multiple chunks of memory can be > * allocated from same window > * @PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC: Indicates only single memory allocation > * is possible on the window > * @PCI_EPC_WINDOW_FLAG_LARGE_ALLOC: Window is used for large memory allocation > * @PCI_EPC_WINDOW_FLAG_SMALL_ALLOC: Window is used for small memory allocation > * @PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC: Window is used for high priority data > * transfers > * @PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC: Window is used for low priority data > * transfers Looks like configuration or policy, not something that belongs in DT. Coupling driver features and DT changes is not good for ABI compatible changes either. I'm hesitant to accept any PCI endpoint binding additions because they don't seem to be completely thought out in terms of supporting different usecases. Rob ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 3/6] of: address: add support to parse PCI outbound-ranges 2019-12-13 8:47 ` [v2 3/6] of: address: add support to parse PCI outbound-ranges Lad Prabhakar 2019-12-13 15:07 ` Rob Herring @ 2019-12-13 21:05 ` Bjorn Helgaas 2019-12-16 8:55 ` Lad, Prabhakar 1 sibling, 1 reply; 27+ messages in thread From: Bjorn Helgaas @ 2019-12-13 21:05 UTC (permalink / raw) To: Lad Prabhakar Cc: Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel, linux-arm-kernel, linux-renesas-soc, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar On Fri, Dec 13, 2019 at 08:47:45AM +0000, Lad Prabhakar wrote: > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> $ git log --oneline drivers/of/address.c 951d48855d86 of: Make of_dma_get_range() work on bus nodes 645c138636de of/address: Fix of_pci_range_parser_one translation of DMA addresses 81db12ee15cb of/address: Translate 'dma-ranges' for parent nodes missing 'dma-ranges' b68ac8dc22eb of: Factor out #{addr,size}-cells parsing c60bf3eb888a of: address: Follow DMA parent for "dma-coherent" 862ab5578f75 of/address: Introduce of_get_next_dma_parent() helper Make yours match. There are a few "of: address: " subjects, but the ones from Rob (the maintainer) use "of/address: ", so I'd use that. > this patch adds support to parse PCI outbound-ranges, the > outbound-regions are similar to pci ranges except it doesn't > have pci address, below is the format for bar-ranges: s/pci/PCI/ Capitalize sentences. Is "bar-range" an actual DT property? If it's supposed to be a generic description, "BAR range" would be better. > outbound-ranges = <flags upper32_cpuaddr lower32_cpuaddr > upper32_size lower32_size>; ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 3/6] of: address: add support to parse PCI outbound-ranges 2019-12-13 21:05 ` Bjorn Helgaas @ 2019-12-16 8:55 ` Lad, Prabhakar 0 siblings, 0 replies; 27+ messages in thread From: Lad, Prabhakar @ 2019-12-16 8:55 UTC (permalink / raw) To: Bjorn Helgaas Cc: Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML, LAK, Linux-Renesas, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar Hi Bjorn, Thank you for the review. On Fri, Dec 13, 2019 at 9:05 PM Bjorn Helgaas <helgaas@kernel.org> wrote: > > On Fri, Dec 13, 2019 at 08:47:45AM +0000, Lad Prabhakar wrote: > > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > $ git log --oneline drivers/of/address.c > 951d48855d86 of: Make of_dma_get_range() work on bus nodes > 645c138636de of/address: Fix of_pci_range_parser_one translation of DMA addresses > 81db12ee15cb of/address: Translate 'dma-ranges' for parent nodes missing 'dma-ranges' > b68ac8dc22eb of: Factor out #{addr,size}-cells parsing > c60bf3eb888a of: address: Follow DMA parent for "dma-coherent" > 862ab5578f75 of/address: Introduce of_get_next_dma_parent() helper > > Make yours match. There are a few "of: address: " subjects, but the > ones from Rob (the maintainer) use "of/address: ", so I'd use that. > will do the same for next iteration. > > this patch adds support to parse PCI outbound-ranges, the > > outbound-regions are similar to pci ranges except it doesn't > > have pci address, below is the format for bar-ranges: > > s/pci/PCI/ > Capitalize sentences. > will fix that. > Is "bar-range" an actual DT property? If it's supposed to be a > generic description, "BAR range" would be better. > my bad, it should be outbound-range. Cheers, --Prabhakar > > outbound-ranges = <flags upper32_cpuaddr lower32_cpuaddr > > upper32_size lower32_size>; ^ permalink raw reply [flat|nested] 27+ messages in thread
* [v2 4/6] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller 2019-12-13 8:47 [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs Lad Prabhakar ` (2 preceding siblings ...) 2019-12-13 8:47 ` [v2 3/6] of: address: add support to parse PCI outbound-ranges Lad Prabhakar @ 2019-12-13 8:47 ` Lad Prabhakar 2019-12-19 23:35 ` Rob Herring 2020-01-03 16:29 ` Lad, Prabhakar 2019-12-13 8:47 ` [v2 5/6] pci: rcar: add support for rcar pcie controller in endpoint mode Lad Prabhakar ` (2 subsequent siblings) 6 siblings, 2 replies; 27+ messages in thread From: Lad Prabhakar @ 2019-12-13 8:47 UTC (permalink / raw) To: Bjorn Helgaas, Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci Cc: Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel, linux-arm-kernel, linux-renesas-soc, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> This patch adds the bindings for the R-Car PCIe endpoint driver. Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- .../devicetree/bindings/pci/rcar-pci-ep.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/rcar-pci-ep.txt diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt b/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt new file mode 100644 index 0000000..7f0a97e --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt @@ -0,0 +1,37 @@ +* Renesas R-Car PCIe Endpoint Controller DT description + +Required properties: + "renesas,pcie-ep-r8a774c0" for the R8A774C0 SoC; + "renesas,pcie-ep-rcar-gen3" for a generic R-Car Gen3 or + RZ/G2 compatible device. + + When compatible with the generic version, nodes must list the + SoC-specific version corresponding to the platform first + followed by the generic version. + +- reg: base address and length of the PCIe controller registers. +- outbound-ranges: outbound windows base address and length including the flags. +- resets: Must contain phandles to PCIe-related reset lines exposed by IP block +- clocks: from common clock binding: clock specifiers for the PCIe controller + clock. +- clock-names: from common clock binding: should be "pcie". + +Optional Property: +- max-functions: Maximum number of functions that can be configured (default 1). + +Example: + +SoC-specific DT Entry: + + pcie_ep: pcie_ep@fe000000 { + compatible = "renesas,pcie-ep-r8a774c0", "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + outbound-ranges = <0xa 0x0 0xfe100000 0 0x000100000 + 0xa 0x0 0xfe200000 0 0x000200000 + 0x6 0x0 0x30000000 0 0x008000000 + 0x6 0x0 0x38000000 0 0x008000000>; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 319>; + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [v2 4/6] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller 2019-12-13 8:47 ` [v2 4/6] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller Lad Prabhakar @ 2019-12-19 23:35 ` Rob Herring 2020-01-02 8:47 ` Lad, Prabhakar 2020-01-03 16:29 ` Lad, Prabhakar 1 sibling, 1 reply; 27+ messages in thread From: Rob Herring @ 2019-12-19 23:35 UTC (permalink / raw) To: Lad Prabhakar Cc: Bjorn Helgaas, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel, linux-arm-kernel, linux-renesas-soc, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar On Fri, Dec 13, 2019 at 08:47:46AM +0000, Lad Prabhakar wrote: > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > This patch adds the bindings for the R-Car PCIe endpoint driver. > > Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > .../devicetree/bindings/pci/rcar-pci-ep.txt | 37 ++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/rcar-pci-ep.txt Please make this a DT schema. > > diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt b/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt > new file mode 100644 > index 0000000..7f0a97e > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt > @@ -0,0 +1,37 @@ > +* Renesas R-Car PCIe Endpoint Controller DT description > + > +Required properties: > + "renesas,pcie-ep-r8a774c0" for the R8A774C0 SoC; Normal ordering is: renesas,r8a774c0-pcie-ep > + "renesas,pcie-ep-rcar-gen3" for a generic R-Car Gen3 or > + RZ/G2 compatible device. > + > + When compatible with the generic version, nodes must list the > + SoC-specific version corresponding to the platform first > + followed by the generic version. > + > +- reg: base address and length of the PCIe controller registers. > +- outbound-ranges: outbound windows base address and length including the flags. > +- resets: Must contain phandles to PCIe-related reset lines exposed by IP block How many? > +- clocks: from common clock binding: clock specifiers for the PCIe controller > + clock. > +- clock-names: from common clock binding: should be "pcie". > + > +Optional Property: > +- max-functions: Maximum number of functions that can be configured (default 1). > + > +Example: > + > +SoC-specific DT Entry: > + > + pcie_ep: pcie_ep@fe000000 { pcie-ep@ > + compatible = "renesas,pcie-ep-r8a774c0", "renesas,pcie-rcar-gen2"; > + reg = <0 0xfe000000 0 0x80000>; > + outbound-ranges = <0xa 0x0 0xfe100000 0 0x000100000 > + 0xa 0x0 0xfe200000 0 0x000200000 > + 0x6 0x0 0x30000000 0 0x008000000 > + 0x6 0x0 0x38000000 0 0x008000000>; > + clocks = <&cpg CPG_MOD 319>; > + clock-names = "pcie"; > + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; > + resets = <&cpg 319>; > + }; > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 4/6] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller 2019-12-19 23:35 ` Rob Herring @ 2020-01-02 8:47 ` Lad, Prabhakar 0 siblings, 0 replies; 27+ messages in thread From: Lad, Prabhakar @ 2020-01-02 8:47 UTC (permalink / raw) To: Rob Herring Cc: Bjorn Helgaas, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML, LAK, Linux-Renesas, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, open list:ARM/Rockchip SoC..., Lad, Prabhakar Hi Rob, Thank you for the review. On Thu, Dec 19, 2019 at 11:35 PM Rob Herring <robh@kernel.org> wrote: > > On Fri, Dec 13, 2019 at 08:47:46AM +0000, Lad Prabhakar wrote: > > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > This patch adds the bindings for the R-Car PCIe endpoint driver. > > > > Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > .../devicetree/bindings/pci/rcar-pci-ep.txt | 37 ++++++++++++++++++++++ > > 1 file changed, 37 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pci/rcar-pci-ep.txt > > Please make this a DT schema. > sure will do. > > > > diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt b/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt > > new file mode 100644 > > index 0000000..7f0a97e > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt > > @@ -0,0 +1,37 @@ > > +* Renesas R-Car PCIe Endpoint Controller DT description > > + > > +Required properties: > > + "renesas,pcie-ep-r8a774c0" for the R8A774C0 SoC; > > Normal ordering is: renesas,r8a774c0-pcie-ep > > > + "renesas,pcie-ep-rcar-gen3" for a generic R-Car Gen3 or > > + RZ/G2 compatible device. > > + > > + When compatible with the generic version, nodes must list the > > + SoC-specific version corresponding to the platform first > > + followed by the generic version. > > + > > +- reg: base address and length of the PCIe controller registers. > > +- outbound-ranges: outbound windows base address and length including the flags. > > +- resets: Must contain phandles to PCIe-related reset lines exposed by IP block > > How many? > should be one. > > +- clocks: from common clock binding: clock specifiers for the PCIe controller > > + clock. > > +- clock-names: from common clock binding: should be "pcie". > > + > > +Optional Property: > > +- max-functions: Maximum number of functions that can be configured (default 1). > > + > > +Example: > > + > > +SoC-specific DT Entry: > > + > > + pcie_ep: pcie_ep@fe000000 { > > pcie-ep@ > will fix that. Cheers, --Prabhakar > > + compatible = "renesas,pcie-ep-r8a774c0", "renesas,pcie-rcar-gen2"; > > + reg = <0 0xfe000000 0 0x80000>; > > + outbound-ranges = <0xa 0x0 0xfe100000 0 0x000100000 > > + 0xa 0x0 0xfe200000 0 0x000200000 > > + 0x6 0x0 0x30000000 0 0x008000000 > > + 0x6 0x0 0x38000000 0 0x008000000>; > > + clocks = <&cpg CPG_MOD 319>; > > + clock-names = "pcie"; > > + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; > > + resets = <&cpg 319>; > > + }; > > -- > > 2.7.4 > > ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 4/6] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller 2019-12-13 8:47 ` [v2 4/6] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller Lad Prabhakar 2019-12-19 23:35 ` Rob Herring @ 2020-01-03 16:29 ` Lad, Prabhakar 1 sibling, 0 replies; 27+ messages in thread From: Lad, Prabhakar @ 2020-01-03 16:29 UTC (permalink / raw) To: Bjorn Helgaas, Rob Herring, Mark Rutland, Kishon Vijay Abraham I Cc: Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Magnus Damm, Marek Vasut, Andrew Murray, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Yoshihiro Shimoda, LKML, LAK, Linux-Renesas, Chris Paterson, Geert Uytterhoeven, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, open list:ARM/Rockchip SoC..., Lad, Prabhakar, linux-pci Hi Kishon/Rob, On Fri, Dec 13, 2019 at 8:48 AM Lad Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> > > This patch adds the bindings for the R-Car PCIe endpoint driver. > > Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > .../devicetree/bindings/pci/rcar-pci-ep.txt | 37 ++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/rcar-pci-ep.txt > > diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt b/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt > new file mode 100644 > index 0000000..7f0a97e > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.txt > @@ -0,0 +1,37 @@ > +* Renesas R-Car PCIe Endpoint Controller DT description > + > +Required properties: > + "renesas,pcie-ep-r8a774c0" for the R8A774C0 SoC; > + "renesas,pcie-ep-rcar-gen3" for a generic R-Car Gen3 or > + RZ/G2 compatible device. > + > + When compatible with the generic version, nodes must list the > + SoC-specific version corresponding to the platform first > + followed by the generic version. > + > +- reg: base address and length of the PCIe controller registers. > +- outbound-ranges: outbound windows base address and length including the flags. > +- resets: Must contain phandles to PCIe-related reset lines exposed by IP block > +- clocks: from common clock binding: clock specifiers for the PCIe controller > + clock. > +- clock-names: from common clock binding: should be "pcie". > + > +Optional Property: > +- max-functions: Maximum number of functions that can be configured (default 1). > + > +Example: > + > +SoC-specific DT Entry: > + > + pcie_ep: pcie_ep@fe000000 { > + compatible = "renesas,pcie-ep-r8a774c0", "renesas,pcie-rcar-gen2"; > + reg = <0 0xfe000000 0 0x80000>; > + outbound-ranges = <0xa 0x0 0xfe100000 0 0x000100000 > + 0xa 0x0 0xfe200000 0 0x000200000 > + 0x6 0x0 0x30000000 0 0x008000000 > + 0x6 0x0 0x38000000 0 0x008000000>; > + clocks = <&cpg CPG_MOD 319>; > + clock-names = "pcie"; > + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; > + resets = <&cpg 319>; > + }; Now that I have dropped "outbound-ranges", do the below bindings look good ? - reg-names: Must include the following names - "apb-base" - Controller base - "memory0" - memory window 0 used by the host to map the pci address locally - "memory1" - memory window 1 used by the host to map the pci address locally - "memory2" - memory window 2 used by the host to map the pci address locally - "memory3" - memory window 3 used by the host to map the pci address locally pcie-ep: pcie_ep@fe000000 { compatible = "renesas,pcie-r8a774c0", "renesas,pcie-rcar-gen2"; reg = <0 0xfe000000 0 0x80000>, <0x0 0xfe100000 0 0x100000>, <0x0 0xfe200000 0 0x200000>, <0x0 0x30000000 0 0x8000000>, <0x0 0x38000000 0 0x8000000>; reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; clocks = <&cpg CPG_MOD 319>; clock-names = "pcie"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 319>; }; Cheers, --Prabhakar ^ permalink raw reply [flat|nested] 27+ messages in thread
* [v2 5/6] pci: rcar: add support for rcar pcie controller in endpoint mode 2019-12-13 8:47 [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs Lad Prabhakar ` (3 preceding siblings ...) 2019-12-13 8:47 ` [v2 4/6] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller Lad Prabhakar @ 2019-12-13 8:47 ` Lad Prabhakar 2019-12-13 8:47 ` [v2 6/6] misc: pci_endpoint_test: add device-id for RZ/G2E pcie controller Lad Prabhakar 2019-12-13 21:06 ` [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs Bjorn Helgaas 6 siblings, 0 replies; 27+ messages in thread From: Lad Prabhakar @ 2019-12-13 8:47 UTC (permalink / raw) To: Bjorn Helgaas, Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci Cc: Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel, linux-arm-kernel, linux-renesas-soc, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> this patch adds support for rcar pcie controller to work in endpoint mode. Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/pci/controller/Kconfig | 7 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-rcar-ep.c | 494 ++++++++++++++++++++++++++++++++++ 3 files changed, 502 insertions(+) create mode 100644 drivers/pci/controller/pcie-rcar-ep.c diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index d3b82f7..41f497c 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -89,6 +89,13 @@ config PCIE_RCAR_HOST help Say Y here if you want PCIe controller support on R-Car SoCs in host mode. +config PCIE_RCAR_EP + bool "Renesas R-Car PCIe endpoint controller" + depends on ARCH_RENESAS || COMPILE_TEST + depends on PCI_ENDPOINT + help + Say Y here if you want PCIe controller support on R-Car SoCs in endpoint mode. + config PCI_HOST_COMMON bool select PCI_ECAM diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index 3577902..16aa1f7 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o +obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o obj-$(CONFIG_PCI_HOST_COMMON) += pci-host-common.o obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c new file mode 100644 index 0000000..c228901 --- /dev/null +++ b/drivers/pci/controller/pcie-rcar-ep.c @@ -0,0 +1,494 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe endpoint driver for Renesas R-Car SoCs + * Copyright (c) 2019 Renesas Electronics Europe GmbH + * + * Author: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of_pci.h> +#include <linux/of_platform.h> +#include <linux/pci.h> +#include <linux/pci-epc.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> + +#include "pcie-rcar.h" + +#define MAX_NR_INBOUND_MAPS 6 +#define MAX_NR_OUTBOUND_MAPS 4 + +/* Structure representing the PCIe interface */ +struct rcar_pcie { + phys_addr_t *ob_addr; + struct pci_epc_mem_window *ob_window; + struct pci_epc *epc; + struct device *dev; + void __iomem *base; + u8 max_functions; + unsigned int bar_to_atu[MAX_NR_INBOUND_MAPS]; + unsigned long *ib_window_map; + u32 num_ib_windows; + u32 num_ob_windows; +}; + +static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) +{ + u32 val; + + rcar_pci_write_reg(pcie->base, 0, PCIETCTLR); + + /* Set endpoint mode */ + rcar_pci_write_reg(pcie->base, 0, PCIEMSR); + + /* Initialize default capabilities. */ + rcar_rmw32(pcie->base, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); + rcar_rmw32(pcie->base, REXPCAP(PCI_EXP_FLAGS), + PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ENDPOINT << 4); + rcar_rmw32(pcie->base, RCONF(PCI_HEADER_TYPE), 0x7f, + PCI_HEADER_TYPE_NORMAL); + + /* Write out the physical slot number = 0 */ + rcar_rmw32(pcie->base, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); + + val = rcar_pci_read_reg(pcie->base, EXPCAP(1)); + /* device supports fixed 128 bytes MPSS */ + val &= ~GENMASK(2, 0); + /* L1 to L0 transition latency no time limit */ + val |= GENMASK(11, 9); + /* L0s to L0 transistion no time limit */ + val |= GENMASK(8, 6); + rcar_pci_write_reg(pcie->base, val, EXPCAP(1)); + + val = rcar_pci_read_reg(pcie->base, EXPCAP(2)); + /* read requests size 128 bytes */ + val &= ~GENMASK(14, 12); + /* payload size 128 bytes */ + val &= ~GENMASK(7, 5); + /* disable relaxed ordering transaction */ + val &= ~BIT(4); + rcar_pci_write_reg(pcie->base, val, EXPCAP(2)); + + val = rcar_pci_read_reg(pcie->base, EXPCAP(4)); + /* disable ASPM control */ + val &= ~GENMASK(1, 0); + rcar_pci_write_reg(pcie->base, val, EXPCAP(4)); + + /* Set target link speed to 5.0 GT/s */ + rcar_rmw32(pcie->base, EXPCAP(12), PCI_EXP_LNKSTA_CLS, + PCI_EXP_LNKSTA_CLS_5_0GB); + + /* Set the completion timer timeout to the maximum 50ms. */ + rcar_rmw32(pcie->base, TLCTLR + 1, 0x3f, 50); + + /* Terminate list of capabilities (Next Capability Offset=0) */ + rcar_rmw32(pcie->base, RVCCAP(0), 0xfff00000, 0); + + /* flush modifications */ + wmb(); +} + +static int rcar_pcie_parse_outbound_ranges(struct rcar_pcie *pcie, + struct platform_device *pdev) +{ + struct of_pci_outbound_range range; + struct of_pci_range_parser parser; + char outbound_name[10]; + struct device_node *np; + unsigned int i = 0; + + np = pdev->dev.of_node; + if (of_pci_outbound_range_parser_init(&parser, np)) + return -EINVAL; + + pcie->num_ob_windows = 0; + /* Get the outbound-ranges from DT */ + for_each_of_pci_outbound_range(&parser, &range) { + sprintf(outbound_name, "memory%u", i); + if (!devm_request_mem_region(&pdev->dev, range.cpu_addr, + range.size, outbound_name)) { + dev_err(pcie->dev, "Cannot request memory region %s.\n", + outbound_name); + return -EIO; + } + + pcie->ob_window[i].phys_base = range.cpu_addr; + pcie->ob_window[i].size = range.size; + pcie->ob_window[i].flags = range.flags; + i++; + } + pcie->num_ob_windows = i; + + return 0; +} + +static int rcar_pcie_ep_get_pdata(struct rcar_pcie *pcie, + struct platform_device *pdev) +{ + struct pci_epc_mem_window *window; + struct device *dev = pcie->dev; + struct resource res; + int err; + + err = of_address_to_resource(dev->of_node, 0, &res); + if (err) + return err; + pcie->base = devm_ioremap_resource(dev, &res); + if (IS_ERR(pcie->base)) + return PTR_ERR(pcie->base); + + pcie->ob_window = devm_kcalloc(dev, MAX_NR_OUTBOUND_MAPS, + sizeof(*window), GFP_KERNEL); + if (!pcie->ob_window) + return -ENOMEM; + + rcar_pcie_parse_outbound_ranges(pcie, pdev); + + err = of_property_read_u8(dev->of_node, "max-functions", + &pcie->max_functions); + if (err < 0) + pcie->max_functions = 1; + + return 0; +} + +static int rcar_pcie_ep_write_header(struct pci_epc *epc, u8 fn, + struct pci_epf_header *hdr) +{ + struct rcar_pcie *ep = epc_get_drvdata(epc); + u32 val; + + if (!fn) + val = hdr->vendorid; + else + val = rcar_pci_read_reg(ep->base, IDSETR0); + val |= hdr->deviceid << DEVICE_ID_SHFIT; + rcar_pci_write_reg(ep->base, val, IDSETR0); + + val = hdr->revid; + val |= hdr->progif_code << 8; + val |= hdr->subclass_code << 16; + val |= hdr->baseclass_code << 24; + rcar_pci_write_reg(ep->base, val, IDSETR1); + + if (!fn) + val = hdr->subsys_vendor_id; + else + val = rcar_pci_read_reg(ep->base, SUBIDSETR); + val |= hdr->subsys_id << 16; + rcar_pci_write_reg(ep->base, val, SUBIDSETR); + + if (hdr->interrupt_pin > PCI_INTERRUPT_INTA) + return -EINVAL; + val = rcar_pci_read_reg(ep->base, PCICONF(15)); + val |= (hdr->interrupt_pin << 8); + rcar_pci_write_reg(ep->base, val, PCICONF(15)); + + return 0; +} + +static int rcar_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, + struct pci_epf_bar *epf_bar) +{ + struct rcar_pcie *ep = epc_get_drvdata(epc); + dma_addr_t cpu_addr = epf_bar->phys_addr; + int flags = epf_bar->flags | LAR_ENABLE | LAM_64BIT; + enum pci_barno bar = epf_bar->barno; + u64 size = 1ULL << fls64(epf_bar->size - 1); + u32 mask; + int idx; + int err; + + idx = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows); + if (idx >= ep->num_ib_windows) { + dev_err(ep->dev, "no free inbound window\n"); + return -EINVAL; + } + + if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) + flags |= IO_SPACE; + + ep->bar_to_atu[bar] = idx; + /* use 64 bit bars */ + set_bit(idx, ep->ib_window_map); + set_bit(idx + 1, ep->ib_window_map); + + if (cpu_addr > 0) { + unsigned long nr_zeros = __ffs64(cpu_addr); + u64 alignment = 1ULL << nr_zeros; + + size = min(size, alignment); + } else { + size = size; + } + + size = min(size, 1ULL << 32); + + mask = roundup_pow_of_two(size) - 1; + mask &= ~0xf; + + rcar_pcie_set_inbound(ep->base, cpu_addr, + 0x0, mask | flags, idx, false); + + err = rcar_pcie_wait_for_phyrdy(ep->base); + if (err) { + dev_err(ep->dev, "phy not ready\n"); + return -EINVAL; + } + + return 0; +} + +static void rcar_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, + struct pci_epf_bar *epf_bar) +{ + struct rcar_pcie *ep = epc_get_drvdata(epc); + enum pci_barno bar = epf_bar->barno; + u32 atu_index = ep->bar_to_atu[bar]; + + rcar_pcie_set_inbound(ep->base, 0x0, 0x0, 0x0, bar, false); + + clear_bit(atu_index, ep->ib_window_map); + clear_bit(atu_index + 1, ep->ib_window_map); +} + +static int rcar_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, + phys_addr_t addr, int window, + u64 pci_addr, size_t size) +{ + struct rcar_pcie *ep = epc_get_drvdata(epc); + struct resource res; + int err; + + /* check if we have a link. */ + err = rcar_pcie_wait_for_dl(ep->base); + if (err) { + dev_err(ep->dev, "link not up\n"); + memset(&res, 0x0, sizeof(res)); + rcar_pcie_set_outbound(window, ep->base, &res, false); + return err; + } + + if (window >= ep->num_ob_windows) { + dev_err(ep->dev, "no free outbound window\n"); + return -EINVAL; + } + + memset(&res, 0x0, sizeof(res)); + res.start = pci_addr; + res.end = pci_addr + size - 1; + res.flags = IORESOURCE_MEM; + + rcar_pcie_set_outbound(window, ep->base, &res, false); + + ep->ob_addr[window] = addr; + + return 0; +} + +static void rcar_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, + phys_addr_t addr) +{ + struct rcar_pcie *ep = epc_get_drvdata(epc); + struct resource res; + int idx; + + for (idx = 0; idx < ep->num_ob_windows; idx++) + if (ep->ob_addr[idx] == addr) + break; + + if (idx >= ep->num_ob_windows) + return; + + memset(&res, 0x0, sizeof(res)); + rcar_pcie_set_outbound(idx, ep->base, &res, false); + + ep->ob_addr[idx] = 0; +} + +static int rcar_pcie_ep_assert_intx(struct rcar_pcie *ep, u8 fn, u8 intx) +{ + u32 val; + + val = rcar_pci_read_reg(ep->base, PCIEMSITXR); + if ((val & PCI_MSI_FLAGS_ENABLE)) { + dev_err(ep->dev, "MSI is enabled, cannot assert INTx\n"); + return -EINVAL; + } + + val = rcar_pci_read_reg(ep->base, PCICONF(1)); + if ((val & INTDIS_SHIFT)) { + dev_err(ep->dev, "INTx message transmission is disabled\n"); + return -EINVAL; + } + + val = rcar_pci_read_reg(ep->base, PCIEINTXR); + if ((val & ASTINTX_SHIFT)) { + dev_err(ep->dev, "INTx is already asserted\n"); + return -EINVAL; + } + + val |= ASTINTX_SHIFT; + rcar_pci_write_reg(ep->base, val, PCIEINTXR); + mdelay(1); + val = rcar_pci_read_reg(ep->base, PCIEINTXR); + val &= ~ASTINTX_SHIFT; + rcar_pci_write_reg(ep->base, val, PCIEINTXR); + + return 0; +} + +static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, + enum pci_epc_irq_type type, + u16 interrupt_num) +{ + struct rcar_pcie *ep = epc_get_drvdata(epc); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + return rcar_pcie_ep_assert_intx(ep, fn, 0); + default: + return -EINVAL; + } +} + +static int rcar_pcie_ep_start(struct pci_epc *epc) +{ + struct rcar_pcie *ep = epc_get_drvdata(epc); + + rcar_pci_write_reg(ep->base, CFINIT, PCIETCTLR); + + return 0; +} + +static void rcar_pcie_ep_stop(struct pci_epc *epc) +{ + struct rcar_pcie *ep = epc_get_drvdata(epc); + + rcar_pci_write_reg(ep->base, 0, PCIETCTLR); +} + +static const struct pci_epc_features rcar_pcie_epc_features = { + .linkup_notifier = false, + .msi_capable = false, + .msix_capable = false, + /* use 64-bit bars so mark bar1/3/5 as reserved */ + .reserved_bar = 1 << BAR_1 | 1 << BAR_3 | 1 << BAR_5, + .bar_fixed_64bit = (1 << BAR_0) | (1 << BAR_2) | (1 << BAR_4), + .bar_fixed_size[0] = 128, + .bar_fixed_size[2] = 256, + .bar_fixed_size[4] = 256, +}; + +static const struct pci_epc_features* +rcar_pcie_ep_get_features(struct pci_epc *epc, u8 func_no) +{ + return &rcar_pcie_epc_features; +} + +static const struct pci_epc_ops rcar_pcie_epc_ops = { + .write_header = rcar_pcie_ep_write_header, + .set_bar = rcar_pcie_ep_set_bar, + .clear_bar = rcar_pcie_ep_clear_bar, + .map_addr = rcar_pcie_ep_map_addr, + .unmap_addr = rcar_pcie_ep_unmap_addr, + .raise_irq = rcar_pcie_ep_raise_irq, + .start = rcar_pcie_ep_start, + .stop = rcar_pcie_ep_stop, + .get_features = rcar_pcie_ep_get_features, +}; + +static const struct of_device_id rcar_pcie_ep_of_match[] = { + { + .compatible = "renesas,pcie-ep-rcar-gen3" + }, + {}, +}; + +static int rcar_pcie_ep_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rcar_pcie *pcie; + struct pci_epc *epc; + int err; + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + pcie->dev = dev; + + pm_runtime_enable(pcie->dev); + err = pm_runtime_get_sync(pcie->dev); + if (err < 0) { + dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); + goto err_pm_disable; + } + + err = rcar_pcie_ep_get_pdata(pcie, pdev); + if (err < 0) { + dev_err(dev, "failed to request resources: %d\n", err); + goto err_pm_put; + } + + pcie->num_ib_windows = MAX_NR_INBOUND_MAPS; + pcie->ib_window_map = + devm_kcalloc(dev, BITS_TO_LONGS(pcie->num_ib_windows), + sizeof(long), GFP_KERNEL); + if (!pcie->ib_window_map) { + err = -ENOMEM; + dev_err(dev, "failed to allocate memory for inbound map\n"); + goto err_pm_put; + } + + pcie->ob_addr = devm_kcalloc(dev, pcie->num_ob_windows, + sizeof(*pcie->ob_addr), GFP_KERNEL); + if (!pcie->ob_addr) { + err = -ENOMEM; + dev_err(dev, "failed to allocate memory for outbound memory pointers\n"); + goto err_pm_put; + } + + epc = devm_pci_epc_create(dev, &rcar_pcie_epc_ops); + if (IS_ERR(epc)) { + dev_err(dev, "failed to create epc device\n"); + err = PTR_ERR(epc); + goto err_pm_put; + } + + epc->max_functions = pcie->max_functions; + pcie->epc = epc; + epc_set_drvdata(epc, pcie); + + err = pci_epc_mem_init(epc, pcie->ob_window, pcie->num_ob_windows); + if (err < 0) { + dev_err(dev, "failed to initialize the epc memory space\n"); + goto err_pm_put; + } + + rcar_pcie_ep_hw_init(pcie); + + return 0; + +err_pm_put: + pm_runtime_put(dev); + +err_pm_disable: + pm_runtime_disable(dev); + + return err; +} + +static struct platform_driver rcar_pcie_ep_driver = { + .driver = { + .name = "rcar-pcie-ep", + .of_match_table = rcar_pcie_ep_of_match, + .suppress_bind_attrs = true, + }, + .probe = rcar_pcie_ep_probe, +}; +builtin_platform_driver(rcar_pcie_ep_driver); -- 2.7.4 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* [v2 6/6] misc: pci_endpoint_test: add device-id for RZ/G2E pcie controller 2019-12-13 8:47 [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs Lad Prabhakar ` (4 preceding siblings ...) 2019-12-13 8:47 ` [v2 5/6] pci: rcar: add support for rcar pcie controller in endpoint mode Lad Prabhakar @ 2019-12-13 8:47 ` Lad Prabhakar 2019-12-13 21:06 ` [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs Bjorn Helgaas 6 siblings, 0 replies; 27+ messages in thread From: Lad Prabhakar @ 2019-12-13 8:47 UTC (permalink / raw) To: Bjorn Helgaas, Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci Cc: Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel, linux-arm-kernel, linux-renesas-soc, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com> Add RZ/G2E in pci_device_id table so that pci-epf-test can be used for testing PCIe EP in RZ/G2E. Signed-off-by: Lad, Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/misc/pci_endpoint_test.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 6e208a0..3e879c7 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -66,6 +66,8 @@ #define PCI_DEVICE_ID_TI_AM654 0xb00c +#define PCI_DEVICE_ID_RENESAS_RZG2E 0x002d + #define is_am654_pci_dev(pdev) \ ((pdev)->device == PCI_DEVICE_ID_TI_AM654) @@ -797,6 +799,7 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654), .driver_data = (kernel_ulong_t)&am654_data }, + { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_RZG2E) }, { } }; MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); -- 2.7.4 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs 2019-12-13 8:47 [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs Lad Prabhakar ` (5 preceding siblings ...) 2019-12-13 8:47 ` [v2 6/6] misc: pci_endpoint_test: add device-id for RZ/G2E pcie controller Lad Prabhakar @ 2019-12-13 21:06 ` Bjorn Helgaas 2019-12-16 9:27 ` Lad, Prabhakar 6 siblings, 1 reply; 27+ messages in thread From: Bjorn Helgaas @ 2019-12-13 21:06 UTC (permalink / raw) To: Lad Prabhakar Cc: Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, devicetree, linux-kernel, linux-arm-kernel, linux-renesas-soc, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, linux-rockchip, Lad, Prabhakar On Fri, Dec 13, 2019 at 08:47:42AM +0000, Lad Prabhakar wrote: > Lad, Prabhakar (6): > pci: pcie-rcar: preparation for adding endpoint support > pci: endpoint: add support to handle features of outbound memory > of: address: add support to parse PCI outbound-ranges > dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint > controller > pci: rcar: add support for rcar pcie controller in endpoint mode > misc: pci_endpoint_test: add device-id for RZ/G2E pcie controller The next time you post this, please update the subject lines to match existing conventions (capitalize "PCI", description is a complete sentence starting with a capitalized verb, etc"). Run "git log --online" on the file you're changing and make yours look the same. s/pci: /PCI: / s/pcie-rcar: /rcar: / s/pcie/PCIe/ s/device-id/Device ID/ ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs 2019-12-13 21:06 ` [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs Bjorn Helgaas @ 2019-12-16 9:27 ` Lad, Prabhakar 0 siblings, 0 replies; 27+ messages in thread From: Lad, Prabhakar @ 2019-12-16 9:27 UTC (permalink / raw) To: Bjorn Helgaas Cc: Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm, Kishon Vijay Abraham I, Marek Vasut, Yoshihiro Shimoda, linux-pci, Catalin Marinas, Will Deacon, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman, Andrew Murray, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML, LAK, Linux-Renesas, Chris Paterson, Frank Rowand, Gustavo Pimentel, Jingoo Han, Simon Horman, Shawn Lin, Tom Joseph, Heiko Stuebner, open list:ARM/Rockchip SoC..., Lad, Prabhakar Hi Bjorn, On Fri, Dec 13, 2019 at 9:06 PM Bjorn Helgaas <helgaas@kernel.org> wrote: > > On Fri, Dec 13, 2019 at 08:47:42AM +0000, Lad Prabhakar wrote: > > > Lad, Prabhakar (6): > > pci: pcie-rcar: preparation for adding endpoint support > > pci: endpoint: add support to handle features of outbound memory > > of: address: add support to parse PCI outbound-ranges > > dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint > > controller > > pci: rcar: add support for rcar pcie controller in endpoint mode > > misc: pci_endpoint_test: add device-id for RZ/G2E pcie controller > > The next time you post this, please update the subject lines to match > existing conventions (capitalize "PCI", description is a complete > sentence starting with a capitalized verb, etc"). Run "git log > --online" on the file you're changing and make yours look the same. > > s/pci: /PCI: / > s/pcie-rcar: /rcar: / > s/pcie/PCIe/ > s/device-id/Device ID/ Thank you for the review, I'll fix the above in next iteration. Cheers, --Prabhakar ^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2020-01-03 16:30 UTC | newest] Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-12-13 8:47 [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs Lad Prabhakar 2019-12-13 8:47 ` [v2 1/6] pci: pcie-rcar: preparation for adding endpoint support Lad Prabhakar 2019-12-13 21:06 ` Bjorn Helgaas 2019-12-16 7:52 ` Lad, Prabhakar 2019-12-13 8:47 ` [v2 2/6] pci: endpoint: add support to handle features of outbound memory Lad Prabhakar 2019-12-13 21:06 ` Bjorn Helgaas 2019-12-16 8:21 ` Lad, Prabhakar 2019-12-16 11:35 ` Kishon Vijay Abraham I 2019-12-18 17:23 ` Lad, Prabhakar 2020-01-02 9:44 ` Kishon Vijay Abraham I 2020-01-02 9:59 ` Lad, Prabhakar 2019-12-13 8:47 ` [v2 3/6] of: address: add support to parse PCI outbound-ranges Lad Prabhakar 2019-12-13 15:07 ` Rob Herring 2019-12-16 8:49 ` Lad, Prabhakar 2019-12-19 23:31 ` Rob Herring 2020-01-02 8:44 ` Lad, Prabhakar 2020-01-02 22:55 ` Rob Herring 2019-12-13 21:05 ` Bjorn Helgaas 2019-12-16 8:55 ` Lad, Prabhakar 2019-12-13 8:47 ` [v2 4/6] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller Lad Prabhakar 2019-12-19 23:35 ` Rob Herring 2020-01-02 8:47 ` Lad, Prabhakar 2020-01-03 16:29 ` Lad, Prabhakar 2019-12-13 8:47 ` [v2 5/6] pci: rcar: add support for rcar pcie controller in endpoint mode Lad Prabhakar 2019-12-13 8:47 ` [v2 6/6] misc: pci_endpoint_test: add device-id for RZ/G2E pcie controller Lad Prabhakar 2019-12-13 21:06 ` [v2 0/6] Add support for PCIe controller to work in endpoint mode on R-Car SoCs Bjorn Helgaas 2019-12-16 9:27 ` Lad, Prabhakar
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).