From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1B47C10F25 for ; Tue, 10 Mar 2020 01:07:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B967424649 for ; Tue, 10 Mar 2020 01:07:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726469AbgCJBHZ (ORCPT ); Mon, 9 Mar 2020 21:07:25 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:21605 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726466AbgCJBHY (ORCPT ); Mon, 9 Mar 2020 21:07:24 -0400 Date: 10 Mar 2020 10:07:23 +0900 X-IronPort-AV: E=Sophos;i="5.70,535,1574089200"; d="scan'208";a="41431033" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 10 Mar 2020 10:07:23 +0900 Received: from mercury.renesas.com (unknown [10.166.252.133]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 2B391400753F; Tue, 10 Mar 2020 10:07:23 +0900 (JST) Message-ID: <87a74pvwz8.wl-kuninori.morimoto.gx@renesas.com> From: Kuninori Morimoto To: Alex Riesen Cc: Laurent Pinchart , Geert Uytterhoeven , Kieran Bingham , Mauro Carvalho Chehab , Hans Verkuil , Rob Herring , Mark Rutland , Driver Development , Linux Media , Linux Kernel , Device Tree , Renesas SoC Subject: Re: [PATCH 8/8] arm64: dts: renesas: salvator: add a connection from adv748x codec (HDMI input) to the R-Car SoC In-Reply-To: <20200309110931.GB3593@pflmari> References: <20200302150706.GB3717@pflmari> <20200302160906.GC3717@pflmari> <20200305143628.GB25741@pflmari> <20200306131632.GA4878@pendragon.ideasonboard.com> <20200306134154.GD27714@pflmari> <20200306134546.GE4878@pendragon.ideasonboard.com> <87r1y2wbze.wl-kuninori.morimoto.gx@renesas.com> <20200309110931.GB3593@pflmari> User-Agent: Wanderlust/2.15.9 Emacs/25.2 Mule/6.0 MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hi Alex > Should the adv748x driver also implement anything to configure the frequency > of MCLK clock? I mean something like .set_sysclk and .set_fmt callbacks of > snd_soc_dai_ops? > > Or is the driver implementation, which depends on mclk-fs to be 256, the audio > stream format to be 8x S24_LE, and requires strictly 48kHz sampling rate on > the HDMI input, a totally acceptable first attempt at writing a DAI driver? > > I'm a bit bothered by that, as the hardware is also capable of decoding > stereo, sampling rate 32-192kHz, a variety of PCM and compressed/encrypted > formats, 128-768fs MCLK multipliers, and a row of I2S options. > > I just find it confusing to place the configuration interfaces. > For instance, the patches use the media ioctl for audio output selection to > select I2S protocol. While works, it does not feel right (shouldn't it be in > the device tree?) > > Maybe you can point me at a driver doing something similar? I'm studying media > drivers now, but not many of them use ASoC interfaces for devices providing a > clock. Or maybe I should better look at sound/soc/...? Setting Sound Clock for all cases/patterns are very complex and difficult actually. (ADV7482 configuration) x (ADG divider / selector) x etc, etc... Thus, Current R-Car sound is assuming that audio_clk_a/b/c/i are providing route clock (= no configuration, fixed clock), and ADG divides it, and provide best clock to each SSIx. Current Salvator/ULCB already have 44.1/48kHz route clock (= CS2000 and Audio_CLK_A), and we can reuse it for all SSIx. Thus, ADV7482 clock is not necessary, I guess ? Or providing specific clock for some case is enough (ADG will automatically select it if necessary). If ADV7482 needs more detail clock settings combination, then, there is no method to adjust to it. We need to consider such system somehow. Thank you for your help !! Best regards --- Kuninori Morimoto