From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 394F3C25B12 for ; Thu, 12 Aug 2021 11:24:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 16FB960041 for ; Thu, 12 Aug 2021 11:24:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236888AbhHLLZG (ORCPT ); Thu, 12 Aug 2021 07:25:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236872AbhHLLYy (ORCPT ); Thu, 12 Aug 2021 07:24:54 -0400 Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [IPv6:2a02:1800:120:4::f00:14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECEE3C061384 for ; Thu, 12 Aug 2021 04:24:27 -0700 (PDT) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:438:1ff1:1071:f524]) by xavier.telenet-ops.be with bizsmtp id gbQR2500Y1gJxCh01bQR3G; Thu, 12 Aug 2021 13:24:25 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mE8oz-002FjN-Bi; Thu, 12 Aug 2021 13:24:25 +0200 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mE8oy-00745H-69; Thu, 12 Aug 2021 13:24:24 +0200 From: Geert Uytterhoeven To: Magnus Damm , Rob Herring Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Laurent Pinchart Subject: [PATCH v2 22/29] arm64: dts: renesas: Add support for M3NULCB with R-Car M3Ne-2G Date: Thu, 12 Aug 2021 13:24:12 +0200 Message-Id: <8e4974f3440ca8f07de6f31c9ed4158baa67c0c3.1628766192.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add support for the Renesas R-Car Starter Kit Pro equipped with an R-Car M3Ne-2 SiP. Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart --- v2: - Add Reviewed-by. --- arch/arm64/boot/dts/renesas/Makefile | 1 + arch/arm64/boot/dts/renesas/r8a779m5-ulcb.dts | 36 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779m5-ulcb.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 5c47615525fc9203..9bee0eab5e2c2577 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -84,5 +84,6 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a779m4-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a779m4-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb +dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-ulcb.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779m5-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a779m5-ulcb.dts new file mode 100644 index 0000000000000000..17242ec02a65ad93 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779m5-ulcb.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) with R-Car M3Ne-2G + * + * Copyright (C) 2021 Glider bv + * + * Based on r8a77965-ulcb.dts + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a779m5.dtsi" +#include "ulcb.dtsi" + +/ { + model = "Renesas M3NULCB board based on r8a779m5"; + compatible = "renesas,m3nulcb", "renesas,r8a779m5", "renesas,r8a77965"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&versaclock5 3>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; -- 2.25.1