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Thu, 08 Sep 2022 05:13:54 -0700 (PDT) MIME-Version: 1.0 References: <20220906102154.32526-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220906102154.32526-2-prabhakar.mahadev-lad.rj@bp.renesas.com> <8ecb62b7-53c4-1c43-65b3-567d8c12e131@microchip.com> In-Reply-To: From: "Lad, Prabhakar" Date: Thu, 8 Sep 2022 13:13:27 +0100 Message-ID: Subject: Re: [RFC PATCH 1/2] riscv: vendors: andes: Add support to configure the PMA regions To: Conor Dooley Cc: guoren@linux.alibaba.com, atishp@atishpatra.org, "Lad, Prabhakar" , Paul Walmsley , Biju Das , Palmer Dabbelt , Albert Ou , atishp@rivosinc.com, apatel@ventanamicro.com, Geert Uytterhoeven , linux-riscv , Linux-Renesas , LKML Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org On Thu, Sep 8, 2022 at 1:00 PM wrote: > > On 08/09/2022 12:50, Lad, Prabhakar wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > Hi Guo, > > > >>> -----Original Message----- > >>> From: Conor.Dooley@microchip.com > >>> Sent: 08 September 2022 00:38 > >>> To: atishp@atishpatra.org > >>> Cc: Prabhakar Mahadev Lad ; > >>> paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > >>> atishp@rivosinc.com; apatel@ventanamicro.com; geert+renesas@glider.be; > >>> linux-riscv@lists.infradead.org; linux-renesas-soc@vger.kernel.org; > >>> linux-kernel@vger.kernel.org; prabhakar.csengg@gmail.com; Biju Das > >>> > >>> Subject: Re: [RFC PATCH 1/2] riscv: vendors: andes: Add support to > >>> configure the PMA regions > >>> > >>> On 07/09/2022 22:52, Atish Patra wrote: > >>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know > >>>> the content is safe > >>>> > >>>> > >>>> On Tue, Sep 6, 2022 at 3:40 AM >>>> > wrote: > >>>> > >>>> On 06/09/2022 11:21, Lad Prabhakar wrote: > >>>> > >>>>> diff --git a/arch/riscv/include/asm/sbi.h > >>>>> b/arch/riscv/include/asm/sbi.h index 2a0ef738695e..10a7c855d125 > >>>>> 100644 --- a/arch/riscv/include/asm/sbi.h +++ > >>>>> b/arch/riscv/include/asm/sbi.h @@ -37,6 +37,7 @@ enum sbi_ext_id { > >>>>> > >>>>> /* Vendor extensions must lie within this range */ > >>>>> SBI_EXT_VENDOR_START = 0x09000000, + SBI_EXT_ANDES = > >>>>> 0x0900031E, SBI_EXT_VENDOR_END = 0x09FFFFFF, }; > >>>> > > I am interested to know what is the status of your patch series [0]. > > > > [0] https://lore.kernel.org/lkml/20210606143848.GA5983@lst.de/T/#m7f4c4cdfb92d6c8672bbfabebda729ce4700e177 > > Heh, take a look at: > git grep "ERRATA_THEAD*" > > This is all can-of-worms territory that we are heading to here, as > the Zicbo* extensions is what is meant to be doing these sorts of > things.. > Aha thanks for the pointer. Cheers, Prabhakar