From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Wolfram Sang <wsa+renesas@sang-engineering.com>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v2 1/2] drivers: clk: renesas: rzg2l-cpg: Add SDHI clk mux support
Date: Fri, 8 Oct 2021 11:46:25 +0200 [thread overview]
Message-ID: <CAMuHMdUD6CEUWnL+PAowN1fAoTpuh6=JXt8gwCgeqH2u0Cpv5A@mail.gmail.com> (raw)
In-Reply-To: <20211007111434.8665-2-biju.das.jz@bp.renesas.com>
Hi Biju,
On Thu, Oct 7, 2021 at 1:14 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add SDHI clk mux support to select SDHI clock from different clock
> sources.
>
> As per HW manual, direct clock switching from 533MHz to 400MHz and
> vice versa is not recommended. So added support for handling this
> in mux.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> This patch depend upon [1]
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20210928130132.15022-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> v1->v2:
> * Removed flags and mux flags
> * Added readl_poll_timeout to check CPG_CLKSTATUS.SELSDHIx_STS bit
> * Added curly braces around val in rzg2l_cpg_sd_clk_mux_get_parent()
Thanks for the update!
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.16.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2021-10-08 9:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-07 11:14 [PATCH v2 0/2] Add SDHI clock and reset entries in cpg driver Biju Das
2021-10-07 11:14 ` [PATCH v2 1/2] drivers: clk: renesas: rzg2l-cpg: Add SDHI clk mux support Biju Das
2021-10-08 9:46 ` Geert Uytterhoeven [this message]
2021-10-07 11:14 ` [PATCH v2 2/2] drivers: clk: renesas: r9a07g044-cpg: Add SDHI clock and reset entries Biju Das
2021-10-08 9:46 ` Geert Uytterhoeven
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