From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC28BC07E95 for ; Fri, 16 Jul 2021 08:57:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9916F613DA for ; Fri, 16 Jul 2021 08:57:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238707AbhGPJAp (ORCPT ); Fri, 16 Jul 2021 05:00:45 -0400 Received: from mail-vs1-f52.google.com ([209.85.217.52]:44703 "EHLO mail-vs1-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239301AbhGPI73 (ORCPT ); Fri, 16 Jul 2021 04:59:29 -0400 Received: by mail-vs1-f52.google.com with SMTP id f4so4571480vsh.11; Fri, 16 Jul 2021 01:56:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=7tHhki3aphTw+T8sH9x98BuGFR0iW2Ee/zuAbvNRS7M=; b=txdR+80+jda/XYaoG4jvUqDWRbhrXRJohcFZnwU294zf0Go7Pt2UrSeNVyubDvX0eu AK2IdzEyIZoj0qnyy99eJm3RHz2XLO0sYM/BXpCJSdRZRTNICZDL9fkF3OHWkYYmdWAK pvkWx51v9551ryyNtczDYMmNcLSGkXI6rfNUbfIWF8Lp+0eN4kjEocpMyz/u9gWtAH5v 59a0kdOoMuYob2LRhWc6I+/zPFKiud5TO9H9jb5wKL69DMhRKaVmDvRa4HGIy3l4XCNl lVcynssYq96PHwWXz7/196faKnlc70xWMv9P+84URboSaSr3bIGvtiFbAVTJpvt+iyi4 fQ6Q== X-Gm-Message-State: AOAM532A4jUXrwJipby2eOR24pm+f+QhN7luGUUgS03RykxoehyruMUj hwCFM3Aktd8SZjJ0EC8UTLXbyuyttQKSoLnMeWI= X-Google-Smtp-Source: ABdhPJzEW1+qMwqxtRATj9Y2pkaijw208kCbHNU65ponKqlood1qioSfjhb9EegcS3SsBrTT8JCYmAIgpF+zayfmhQE= X-Received: by 2002:a67:1542:: with SMTP id 63mr11596800vsv.40.1626425794458; Fri, 16 Jul 2021 01:56:34 -0700 (PDT) MIME-Version: 1.0 References: <20210715182123.23372-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20210715182123.23372-4-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Fri, 16 Jul 2021 10:56:23 +0200 Message-ID: Subject: Re: [PATCH 3/6] dt-bindings: clk: r9a07g044-cpg: Add entry for P0_DIV2 core clock To: "Lad, Prabhakar" Cc: Lad Prabhakar , Rob Herring , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Jakub Kicinski , Michael Turquette , Stephen Boyd , Philipp Zabel , linux-can@vger.kernel.org, netdev , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-clk , Linux Kernel Mailing List , Linux-Renesas , Biju Das Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hi Prabhakar, On Fri, Jul 16, 2021 at 10:45 AM Lad, Prabhakar wrote: > On Fri, Jul 16, 2021 at 9:08 AM Geert Uytterhoeven wrote: > > On Thu, Jul 15, 2021 at 8:21 PM Lad Prabhakar > > wrote: > > > Add P0_DIV2 core clock required for CANFD module. CANFD core clock is > > > sourced from P0_DIV2 referenced from HW manual Rev.0.50. > > > > OK. > > > > > Also add R9A07G044_LAST_CORE_CLK entry to avoid changes in > > > r9a07g044-cpg.c file. > > > > I'm not so fond of adding this. Unlike the other definitions, it is > > not really part of the bindings, but merely a convenience definition > > for the driver. Furthermore it has to change when a new definition > > is ever added. > > > Agreed will drop this. > > > > Signed-off-by: Lad Prabhakar > > > Reviewed-by: Biju Das > > > --- > > > include/dt-bindings/clock/r9a07g044-cpg.h | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > > > diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h > > > index 0728ad07ff7a..2fd20db0b2f4 100644 > > > --- a/include/dt-bindings/clock/r9a07g044-cpg.h > > > +++ b/include/dt-bindings/clock/r9a07g044-cpg.h > > > @@ -30,6 +30,8 @@ > > > #define R9A07G044_CLK_P2 19 > > > #define R9A07G044_CLK_AT 20 > > > #define R9A07G044_OSCCLK 21 > > > +#define R9A07G044_CLK_P0_DIV2 22 > > > +#define R9A07G044_LAST_CORE_CLK 23 > > > > Third issue: off-by-one error, it should be 22 ;-) > > > 23 was intentionally as these numbers aren't used for core clock count > we use r9a07g044_core_clks[] instead. It ends up as an off-by-one bug in the range check in rzg2l_cpg_clk_src_twocell_get(). > Said that I'll drop this. OK. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds