From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 091D2C4338F for ; Mon, 26 Jul 2021 13:25:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D7BCE60F57 for ; Mon, 26 Jul 2021 13:25:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233521AbhGZMov (ORCPT ); Mon, 26 Jul 2021 08:44:51 -0400 Received: from mail-vk1-f180.google.com ([209.85.221.180]:35625 "EHLO mail-vk1-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232572AbhGZMou (ORCPT ); Mon, 26 Jul 2021 08:44:50 -0400 Received: by mail-vk1-f180.google.com with SMTP id i26so2013743vkk.2; Mon, 26 Jul 2021 06:25:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=iiK1bEfZv0REyFeZQ6eGnheFa6agVqoobWMIj2sCXMM=; b=BUAaXbWyaea+TAdXGje71lH1LmPH5lRnbXWr2uJubVt1CLc+2pbroEzCylgLNEkxHh ZcJzPqfFBKSY1EXnNvcgkRcf5jDPC15tAq9ibx+QDPQx8UrV3PAFM2r9afDVAaNJuNac AYiVCRuf+pE6evMh2S4Rh1scrz830u0IylAYslXt4sGIc8b4Aps+KltoCSjahsK2xxdi Vl1L6o9xyxpCaCFzywAaw9uTa5TnClgKO8g6yaooc19ZtXZzeRiCRMwTp/yRlkQLVRy0 wMVOVLHH3ZeCQO7uvUmKB7Vx3u73x6RoZvty09mw6/88l0Hco01Ax3zWb4DfSd16qizq o6hQ== X-Gm-Message-State: AOAM531Eb7x2OB78IMBwwQ+GoMSORGUDkJ2rYSnYMDl3MndsUsewkqQA Ebru/gC0upMiVWkXVzPYaKbJHMeEhySWLyFCuHM= X-Google-Smtp-Source: ABdhPJwOmNw+NUdyRa6fs6Yd24Srzz7LWuqCJoocbSYcr4aZR7cGIgHsBgXk63yc6Xppks8q98hgWQwqMuuVn+gfchs= X-Received: by 2002:ac5:cd9b:: with SMTP id i27mr10079261vka.1.1627305918978; Mon, 26 Jul 2021 06:25:18 -0700 (PDT) MIME-Version: 1.0 References: <20210721191558.22484-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20210721191558.22484-3-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20210721191558.22484-3-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Mon, 26 Jul 2021 15:25:07 +0200 Message-ID: Subject: Re: [PATCH v3 2/4] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver To: Lad Prabhakar Cc: Rob Herring , Linus Walleij , Magnus Damm , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux-Renesas , Linux Kernel Mailing List , Prabhakar , Biju Das Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hi Prabhakar, On Wed, Jul 21, 2021 at 9:16 PM Lad Prabhakar wrote: > Add support for pin and gpio controller driver for RZ/G2L SoC. > > Based on a patch in the BSP by Hien Huynh . > > Signed-off-by: Lad Prabhakar > Reviewed-by: Biju Das Thanks for the update! > --- /dev/null > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH | \ > + PIN_CFG_SR | \ > + PIN_CFG_PUPD | \ > + PIN_CFG_FILONOFF | \ > + PIN_CFG_FILNUM | \ > + PIN_CFG_FILCLKSEL) > + > +#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ > + PIN_CFG_FILONOFF | \ > + PIN_CFG_FILNUM | \ > + PIN_CFG_FILCLKSEL) I thought you were going for MULTI? ;-) > + > +/* > + * n indicates number of pins in the port, a is the register index > + * and f is pin configuration capabilities supported. > + */ > +#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) > +#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) >> 28) & 0x7) > +#define RZG2L_GPIO_PORT_GET_INDEX(x) ((((x) & GENMASK(27, 20)) >> 20) & 0x7f) Actually the "& 0x7f" can be removed, too, if you adjust the mask: (((x) & GENMASK(26, 20)) >> 20) > +#define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) > + > +/* > + * BIT(31) indicates dedicated pin, p is the register index while > + * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits > + * (b * 8) and f is the pin configuration capabilities supported. > + */ > +#define RZG2L_SINGLE_PIN BIT(31) > +#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ > + ((p) << 24) | ((b) << 20) | (f)) > +#define RZG2L_SINGLE_PIN_GET_PORT(x) (((x) >> 24) & 0x7f) > +#define RZG2L_SINGLE_PIN_GET_BIT(x) ((((x) & GENMASK(23, 20)) >> 20) & 0x7) Likewise: (((x) & GENMASK(22, 20)) >> 20) > +#define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) > + struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); > + struct function_desc *func; > + unsigned int i, *psel_val; > + struct group_desc *group; > + unsigned long data; > + int *pins; > + > + func = pinmux_generic_get_function(pctldev, func_selector); > + if (!func) > + return -EINVAL; > + group = pinctrl_generic_get_group(pctldev, group_selector); > + if (!group) > + return -EINVAL; > + > + psel_val = func->data; > + pins = group->pins; > + data = (unsigned long)group->data; Lkp reports data is unused. Which matches with passing NULL as the last parameter of pinctrl_generic_add_group(). > + > + for (i = 0; i < group->num_pins; i++) { > + dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", > + RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]), > + psel_val[i]); > + rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]), > + RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]); > + } > + > + return 0; > +}; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds