From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50953C3A5A9 for ; Mon, 4 May 2020 14:29:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C6D020757 for ; Mon, 4 May 2020 14:29:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729092AbgEDO3m (ORCPT ); Mon, 4 May 2020 10:29:42 -0400 Received: from mail-ot1-f65.google.com ([209.85.210.65]:35423 "EHLO mail-ot1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729060AbgEDO3m (ORCPT ); Mon, 4 May 2020 10:29:42 -0400 Received: by mail-ot1-f65.google.com with SMTP id k110so4504853otc.2; Mon, 04 May 2020 07:29:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=4qmNWbZEWGK3APAzYwIeRF7N4Ey8Oknk1ZvcU1u1ZqU=; b=N1oXyP7br7VE+24jMnpp//tEsI2I9XMyipiwrWkWyV0WlxffaFdZWcngd8JXS1pXP4 /6ighEpGKEP276G12e4Pu0JNaLUnWjHgTK6cbnaqvYkYNnROtka1WSFPI+u631GQpSWo j/qX4TSs7AWDXwKmOOK5MCtz/OcYRe+prCpD9/QFZNd7+gcGnJfVIwENZ2Sg00uMeVzh lZ2mBJ8OxZtgGMNJHj4DQxSq6Txc+7+ppz3xhoAhNlsx5Rf6YAVaxwZ/MqKzJsuEYJNX 5GGcBolqiK1c5HVmUvZ5chSXUv+OKPPXa1+Y5KZYL1/eEbU27l6ZKz1WvUwwQjtKjDBV IvvA== X-Gm-Message-State: AGi0PuYY/E3WPj86DYzI8Lv6+XTmM+aw9qLH865psgy4eTdcKEb2H2hi npNwSZIpNgFJft8rgPTu77NOvfq5q98kkxjqZbo= X-Google-Smtp-Source: APiQypIl5oeOYwC1jEI/m9PhRtWzOpl25bOP4xHlOC6xhIPb9atAy1P1nyb7qKk0U0HPJufqUAievgfEuM+jpmQcYow= X-Received: by 2002:a9d:7990:: with SMTP id h16mr14016322otm.145.1588602579133; Mon, 04 May 2020 07:29:39 -0700 (PDT) MIME-Version: 1.0 References: <1588542414-14826-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> <1588542414-14826-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Mon, 4 May 2020 16:29:28 +0200 Message-ID: Subject: Re: [PATCH v2 09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM To: "Lad, Prabhakar" Cc: Lad Prabhakar , Magnus Damm , Rob Herring , Vinod Koul , Ulf Hansson , Linus Walleij , Greg Kroah-Hartman , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , dmaengine , Linux MMC List , "open list:GPIO SUBSYSTEM" , "open list:SERIAL DRIVERS" Content-Type: text/plain; charset="UTF-8" Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hi Prabhakar, On Mon, May 4, 2020 at 4:20 PM Lad, Prabhakar wrote: > On Mon, May 4, 2020 at 2:01 PM Geert Uytterhoeven wrote: > > On Sun, May 3, 2020 at 11:48 PM Lad Prabhakar > > wrote: > > > Add support for iWave RZ/G1H Qseven System On Module. > > > > > > Signed-off-by: Lad Prabhakar > > > Reviewed-by: Marian-Cristian Rotariu > > > --- /dev/null > > > +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi > > > @@ -0,0 +1,53 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +/* > > > + * Device Tree Source for the iWave RZ/G1H Qseven SOM > > > + * > > > + * Copyright (C) 2020 Renesas Electronics Corp. > > > + */ > > > + > > > +#include "r8a7742.dtsi" > > > +#include > > > + > > > +/ { > > > + compatible = "iwave,g21m", "renesas,r8a7742"; > > > + > > > + memory@40000000 { > > > + device_type = "memory"; > > > + reg = <0 0x40000000 0 0x40000000>; > > > + }; > > > + > > > + memory@200000000 { > > > + device_type = "memory"; > > > + reg = <2 0x00000000 0 0x20000000>; > > > > According to the schematics, the second bank is also 1 GiB, so the > > reg length should be 0x40000000. > > > Agreed will fix that. Thanks for the confirmation. I can fix that while applying. > > > + }; > > > > > +&pfc { > > > + mmc1_pins: mmc1 { > > > + groups = "mmc1_data4", "mmc1_ctrl"; > > > + function = "mmc1"; > > > + }; > > > +}; > > > + > > > +&mmcif1 { > > > + pinctrl-0 = <&mmc1_pins>; > > > + pinctrl-names = "default"; > > > + > > > + vmmc-supply = <®_3p3v>; > > > + bus-width = <4>; > > > + non-removable; > > > + status = "okay"; > > > +}; > > > > The eMMC has an 8-bit data path. Is there any specific reason you use > > bus-width = <4>, and the "mmc1_data4" pin group? > > > MMC1_DATA7 is shared with VI1_CLK, so instead of limiting to only one > device when using 8-bit just switched to 4bit mode so that both the > peripherals can be used. OK. Reviewed-by: Geert Uytterhoeven i.e. will queue in renesas-devel for v5.8 with the above fixed. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds