From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Wolfgang Grandegger <wg@grandegger.com>,
Marc Kleine-Budde <mkl@pengutronix.de>,
"David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
linux-can@vger.kernel.org, netdev <netdev@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4/6] clk: renesas: r9a07g044-cpg: Add entry for fixed clock P0_DIV2
Date: Fri, 16 Jul 2021 10:09:40 +0200 [thread overview]
Message-ID: <CAMuHMdXYfAxvdRyn0FaqYSyD4qD2P=Et4-d3bPan9oy_YJ7tfg@mail.gmail.com> (raw)
In-Reply-To: <20210715182123.23372-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Thu, Jul 15, 2021 at 8:21 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add entry for fixed core clock P0_DIV2 and assign LAST_DT_CORE_CLK
> to R9A07G044_LAST_CORE_CLK.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a07g044-cpg.c
> +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> @@ -16,7 +16,7 @@
>
> enum clk_ids {
> /* Core Clock Outputs exported to DT */
> - LAST_DT_CORE_CLK = R9A07G044_OSCCLK,
> + LAST_DT_CORE_CLK = R9A07G044_LAST_CORE_CLK,
Please use R9A07G044_CLK_P0_DIV2 instead.
>
> /* External Input Clocks */
> CLK_EXTAL,
> @@ -77,6 +77,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
> DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
> DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
> dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
> + DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
> DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
> DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
> DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
The rest looks good to me.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2021-07-16 8:09 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-15 18:21 [PATCH 0/6] Renesas RZ/G2L CANFD support Lad Prabhakar
2021-07-15 18:21 ` [PATCH 1/6] dt-bindings: net: can: renesas,rcar-canfd: Document RZ/G2L SoC Lad Prabhakar
2021-07-16 7:38 ` Geert Uytterhoeven
2021-07-16 8:30 ` Lad, Prabhakar
2021-07-15 18:21 ` [PATCH 2/6] can: rcar_canfd: Add support for RZ/G2L family Lad Prabhakar
2021-07-16 7:47 ` Geert Uytterhoeven
2021-07-16 8:32 ` Lad, Prabhakar
2021-07-16 10:10 ` Marc Kleine-Budde
2021-07-15 18:21 ` [PATCH 3/6] dt-bindings: clk: r9a07g044-cpg: Add entry for P0_DIV2 core clock Lad Prabhakar
2021-07-16 8:07 ` Geert Uytterhoeven
2021-07-16 8:45 ` Lad, Prabhakar
2021-07-16 8:56 ` Geert Uytterhoeven
2021-07-16 9:02 ` Lad, Prabhakar
2021-07-15 18:21 ` [PATCH 4/6] clk: renesas: r9a07g044-cpg: Add entry for fixed clock P0_DIV2 Lad Prabhakar
2021-07-16 8:09 ` Geert Uytterhoeven [this message]
2021-07-16 8:46 ` Lad, Prabhakar
2021-07-15 18:21 ` [PATCH 5/6] clk: renesas: r9a07g044-cpg: Add clock and reset entries for CANFD Lad Prabhakar
2021-07-16 7:55 ` Geert Uytterhoeven
2021-07-15 18:21 ` [PATCH 6/6] arm64: dts: renesas: r9a07g044: Add CANFD node Lad Prabhakar
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