From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCC16C433DB for ; Wed, 13 Jan 2021 13:26:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 93609233EA for ; Wed, 13 Jan 2021 13:26:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726118AbhAMN0f (ORCPT ); Wed, 13 Jan 2021 08:26:35 -0500 Received: from mail-ot1-f46.google.com ([209.85.210.46]:44949 "EHLO mail-ot1-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726003AbhAMN0f (ORCPT ); Wed, 13 Jan 2021 08:26:35 -0500 Received: by mail-ot1-f46.google.com with SMTP id r9so1821727otk.11 for ; Wed, 13 Jan 2021 05:26:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=o0roQCCO/etbX4RjBdnrG+Olfz1Vs5jFO/h9JUfsdnw=; b=f4q/Ai9CCBjs0lHjPIYffICjQFq+kiDg3OrOIuAAZ/y0XceHcVGWpTrnmZwY6OcBWX Cy815rosFMgUmJQJdgpN37nQKNWjz/NtAo4F/HgU13Wfige2iJvjYHc/gvcGPWwvNI5e 9l5EiI8GIwL1rMSndSMdmFCK2Jkec2Uj9CBR4UbXtCi2YDzAkW9+FE943TBfQQBN1hRk j6kXmw412k1fhrLXJPP9dg4uTmF8tDx8ejtVKmvJkEaxmO8Sw3ll70P+6zm1MqHAp8/U SHveWffFNEiCaGj89gyM8ahM76Kx5kjVsiaRfBYhyTY2fa0PLIPtiu9WyBwTkZgcXfhY X60w== X-Gm-Message-State: AOAM531Mg4AKWM8y73Xp3nnvjywbpFOMb9q1TF1V4njgXFkBrdlneuJK YbZ1WTRgoEYyicArWFLVOzu/LjgsuUJp+tcUMfrD9qj8 X-Google-Smtp-Source: ABdhPJz45dOq/g/gRYmKbZ8JKS87Qr+0oFeWhXsrUVVa9KdhYoDYtwcI2+5rJPng94UVo5bwXIQIECDMiKX0D/gP66k= X-Received: by 2002:a05:6830:1f5a:: with SMTP id u26mr1212955oth.250.1610544354587; Wed, 13 Jan 2021 05:25:54 -0800 (PST) MIME-Version: 1.0 References: <20210112165912.30876-1-uli+renesas@fpond.eu> <20210112165912.30876-2-uli+renesas@fpond.eu> In-Reply-To: <20210112165912.30876-2-uli+renesas@fpond.eu> From: Geert Uytterhoeven Date: Wed, 13 Jan 2021 14:25:43 +0100 Message-ID: Subject: Re: [PATCH v3 1/6] pinctrl: renesas: implement unlock register masks To: Ulrich Hecht Cc: Linux-Renesas , Wolfram Sang , hoai.luu.ub@renesas.com, Wolfram Sang Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org On Tue, Jan 12, 2021 at 5:59 PM Ulrich Hecht wrote: > The V3U SoC has several unlock registers, one per register group. They > reside at offset zero in each 0x200 bytes-sized block. > > To avoid adding yet another table to the PFC implementation, this > patch adds the option to specify an address mask instead of the fixed > address in sh_pfc_soc_info::unlock_reg. > > Signed-off-by: Ulrich Hecht > Tested-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven i.e. will queue in renesas-pinctrl-for-v5.12. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds