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[209.85.219.169]) by smtp.gmail.com with ESMTPSA id h22-20020a05622a171600b0035ba366cc90sm368019qtk.15.2022.09.20.12.24.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 Sep 2022 12:24:17 -0700 (PDT) Received: by mail-yb1-f169.google.com with SMTP id 125so4823836ybt.12; Tue, 20 Sep 2022 12:24:17 -0700 (PDT) X-Received: by 2002:a25:8e84:0:b0:696:466c:baa with SMTP id q4-20020a258e84000000b00696466c0baamr19432910ybl.604.1663701857015; Tue, 20 Sep 2022 12:24:17 -0700 (PDT) MIME-Version: 1.0 References: <20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Tue, 20 Sep 2022 21:24:05 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 00/10] Add support for Renesas RZ/Five SoC To: Conor Dooley Cc: Prabhakar , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Conor Dooley , Heiko Stuebner , Heinrich Schuchardt , Atish Patra , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hi Conor, On Tue, Sep 20, 2022 at 9:20 PM Conor Dooley wrote: > On Tue, Sep 20, 2022 at 07:48:54PM +0100, Prabhakar wrote: > > From: Lad Prabhakar > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > > entry-class social infrastructure gateway control and industrial gateway > > control. > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five > > (R9A07G043) SoC and updates the bindings for the same. Below is the list > > of IP blocks added in the initial SoC DTSI which can be used to boot via > > initramfs on RZ/Five SMARC EVK: > > - AX45MP CPU > > - CPG > > - PINCTRL > > - PLIC > > - SCIF0 > > - SYSC > > Ran into one complaint from dtbs_check: > arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c50200: '#phy-cells' is a required property > From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml > arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c70200: '#phy-cells' is a required property > From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml > > Other than that which should be a trivial fix the whole lot looks good > to me... That's due to the placeholders... Currently it is not yet a requirement that "make dtbs_check" is warning-free. I'm wondering how we have to handle new SoCs with existing boards in the future. Probably just more properties in the placeholders... Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds