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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: RE: [PATCH v2 07/11] drivers: clk: renesas: r9a07g044-cpg: Update {GIC,IA55,SCIF} clock/reset entries
Date: Fri, 25 Jun 2021 18:32:58 +0000	[thread overview]
Message-ID: <OS0PR01MB5922026BB003F14B6260992686069@OS0PR01MB5922.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <CAMuHMdXic7vHg=-OaZ-CSzZjjideTzggitg9pz7xsLMdFH07qQ@mail.gmail.com>

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v2 07/11] drivers: clk: renesas: r9a07g044-cpg: Update
> {GIC,IA55,SCIF} clock/reset entries
> 
> Hi Biju,
> 
> On Fri, Jun 25, 2021 at 6:08 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > Subject: Re: [PATCH v2 07/11] drivers: clk: renesas: r9a07g044-cpg:
> > > Update {GIC,IA55,SCIF} clock/reset entries On Thu, Jun 24, 2021 at
> > > 3:03 PM Biju Das <biju.das.jz@bp.renesas.com>
> > > wrote:
> > > > Update {GIC,IA55,SCIF} clock and reset entries to CPG driver to
> > > > match with RZ/G2L clock list hardware
> > > > manual(RZG2L_clock_list_r02_02.xlsx)
> > > > and RZ/G2L HW manual(Rev.0.50).
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > Reviewed-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> > > > --- a/drivers/clk/renesas/renesas-rzg2l-cpg.h
> > > > +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.h
> > > > @@ -78,7 +78,6 @@ enum clk_types {
> > > >   * @parent: id of parent clock
> > > >   * @off: register offset
> > > >   * @onoff: ON/MON bits
> > > > - * @reset: reset bits
> > > >   */
> > > >  struct rzg2l_mod_clk {
> > > >         const char *name;
> > > > @@ -86,17 +85,15 @@ struct rzg2l_mod_clk {
> > > >         unsigned int parent;
> > > >         u16 off;
> > > >         u8 onoff;
> > > > -       u8 reset;
> > > >  };
> > > >
> > > > -#define DEF_MOD(_name, _id, _parent, _off, _onoff, _reset)     \
> > > > +#define DEF_MOD(_name, _id, _parent, _off, _onoff)     \
> > > >         [_id] = { \
> > >
> > > Hadn't realized this before, but do you need the "[_id] ="?
> > > rzg2l_cpg_info.mod_clks[] is only indexed during initialization.
> > > If there are gaps due to not all clocks being implemented yet, they
> > > are skipped by the .name check in rzg2l_cpg_register_mod_clk().
> > > But I think you can just remove the gaps instead, decreasing kernel
> > > size (for now).
> >
> > That means we need to loop through the array and find out the index
> corresponding to the ID.
> >
> > Current implementation, we don't need to find out ID iterating through
> > LUT. But as you said it is at the expense of kernel memory.
> >
> > Speed vs memory. Long term any way we will fill the holes. The max index
> now is 96.
> 
> Unless I'm missing something, this array is only used for initializing the
> clocks?  Clock lookup by ID is done using rzg2l_cpg_priv.clks[], which is
> indexed by ID.

Geert, you are correct. _Id can be removed.

Regards,
Biju

  reply	other threads:[~2021-06-25 18:33 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-24 13:02 [PATCH v2 00/11] Update clock definitions Biju Das
2021-06-24 13:02 ` [PATCH v2 01/11] drivers: clk: renesas: renesas-rzg2l-cpg: Add multi clock PM support Biju Das
2021-06-24 13:02 ` [PATCH v2 02/11] drivers: clk: renesas: r9a07g044-cpg: Rename divider table Biju Das
2021-06-25 14:27   ` Geert Uytterhoeven
2021-06-25 14:52     ` Biju Das
2021-06-24 13:02 ` [PATCH v2 03/11] drivers: clk: renesas: r9a07g044-cpg: Fix P1 Clock Biju Das
2021-06-25 14:32   ` Geert Uytterhoeven
2021-06-24 13:02 ` [PATCH v2 04/11] drivers: clk: renesas: r9a07g044-cpg: Add P2 Clock support Biju Das
2021-06-25 14:33   ` Geert Uytterhoeven
2021-06-24 13:02 ` [PATCH v2 05/11] dt-bindings: clk: r9a07g044-cpg: Update clock/reset definitions Biju Das
2021-06-25 14:33   ` Geert Uytterhoeven
2021-06-24 13:02 ` [PATCH v2 06/11] drivers: clk: renesas: renesas-rzg2l-cpg: Separate reset from module clocks Biju Das
2021-06-25 14:42   ` Geert Uytterhoeven
2021-06-25 14:50     ` Biju Das
2021-06-24 13:02 ` [PATCH v2 07/11] drivers: clk: renesas: r9a07g044-cpg: Update {GIC,IA55,SCIF} clock/reset entries Biju Das
2021-06-25 15:05   ` Geert Uytterhoeven
2021-06-25 16:08     ` Biju Das
2021-06-25 17:42       ` Geert Uytterhoeven
2021-06-25 18:32         ` Biju Das [this message]
2021-06-24 13:02 ` [PATCH v2 08/11] arm64: dts: renesas: r9a07g044: Update SCIF0 clock/reset Biju Das
2021-06-25 15:05   ` Geert Uytterhoeven
2021-06-24 13:02 ` [PATCH v2 09/11] drivers: clk: renesas: r9a07g044-cpg: Add I2C clocks/resets Biju Das
2021-06-25 15:06   ` Geert Uytterhoeven
2021-06-24 13:02 ` [PATCH v2 10/11] drivers: clk: renesas: r9a07g044-cpg: Add DMAC clocks/resets Biju Das
2021-06-25 15:12   ` Geert Uytterhoeven
2021-06-24 13:02 ` [PATCH v2 11/11] arm64: dts: renesas: r9a07g044: Add I2C nodes Biju Das
2021-06-25 15:16   ` Geert Uytterhoeven
2021-06-25 17:01     ` Biju Das

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