[PATCH v6 0/3] Add USB2.0 support

[PATCH v6 0/3] Add USB2.0 support

[Biju Das]

This patch series aims to add USB2.0 Host and device support for RZ/G2L SoC.

This patch series is based on renesas-devel.

v5->v6:
 * Updated phyrst node with status disabled
 * Added Geert's Rb tag for SoC dtsi patches
 * Sorted defconfig patch alphabetically.
 * Removed USB2.0 phy driver/binding patches as it is accepted for phy/next
 * Removed USBHS binding patches as it is accepted for usb/next.
v4->v5:
 * Removed USBPHY control and binding patches as it is accepted for reset/next
 * Removed USB ehci/ohci binding patches as it is accepted for usb/next.
 * Updated Renesas USB2.0 PHY bindings to just use 'resets' as required.
 * Added interrupts maxitems=1 for SoC other than RZ/G2L for Renesas USBHS bindings
 * Updated the commit description for USB2.0 PHY driver patch.

v3->v4:
 * Added Rob's Acked-by tag for generic-{ohci,ehci} binding patch
 * Added Rob's Rb tag for RZ/G2L USBPHY control binding patch
 * Incorporated Phillip's review comments for USBPHY control driver.
 * Dropped second reset from usb2-phy binding patch
 * Added maxitems as per Rob's review comment.

v2->v3
 * USBPHY Control IP modelled as reset bindings as per Rob's suggestion
 * Updated the binding patches
 * Incorporated Geert's and Shimoda-San's review comment for phy driver patch.

v1->v2
 * Updated usb phy control bindings with clock definitions
 * Updated generic ohci/ehci bindings to support RZ/G2L SoC
 * Incorporated vinod's review comment on usb phy control driver
 * Add support for USB2.0 device and OTG support.

Biju Das (3):
  arm64: defconfig: Enable RZ/G2L USBPHY control driver
  arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support
  arm64: dts: renesas: r9a07g044: Add USB2.0 device support

 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 114 +++++++++++++++++++++
 arch/arm64/configs/defconfig               |   1 +
 2 files changed, 115 insertions(+)

-- 
2.17.1

[PATCH v6 1/3] arm64: defconfig: Enable RZ/G2L USBPHY control driver

[Biju Das]

RZ/G2L SoC supports USBPHY control,so enable it in ARM64 defconfig.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v5->v6:
 * Sorted alphabetically.
v4->v5:
 * No dependencies now. Binding and driver patches accepted for reset/next
v3->v4:
 * No Change.
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c7cf0d1ad34e..0db4925fb788 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1102,6 +1102,7 @@ CONFIG_QCOM_PDC=y
 CONFIG_RESET_IMX7=y
 CONFIG_RESET_QCOM_AOSS=y
 CONFIG_RESET_QCOM_PDC=m
+CONFIG_RESET_RZG2L_USBPHY_CTRL=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_PHY_XGENE=y
 CONFIG_PHY_SUN4I_USB=y
-- 
2.17.1

[PATCH v6 2/3] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support

[Biju Das]

Add USB2.0 phy and host support to SoC DT.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v5->v6:
 * Updated phyrst node with status disabled
 * Added Rb tag from Geert.
v4->v5:
 * No change.
V3->v4:
 * Removed second reset from phy node.
 V3:
  * Added reset entries
  * Updated compatible, phy and reset entries.
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 95 ++++++++++++++++++++++
 1 file changed, 95 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index d50ffce5a74e..de78c921af22 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -296,6 +296,101 @@
 			      <0x0 0x11940000 0 0x60000>;
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 		};
+
+		phyrst: usbphy-ctrl@11c40000 {
+			compatible = "renesas,r9a07g044-usbphy-ctrl",
+				     "renesas,rzg2l-usbphy-ctrl";
+			reg = <0 0x11c40000 0 0x10000>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+			resets = <&cpg R9A07G044_USB_PRESETN>;
+			power-domains = <&cpg>;
+			#reset-cells = <1>;
+			status = "disabled";
+		};
+
+		ohci0: usb@11c50000 {
+			compatible = "generic-ohci";
+			reg = <0 0x11c50000 0 0x100>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+			resets = <&phyrst 0>,
+				 <&cpg R9A07G044_USB_U2H0_HRESETN>;
+			phys = <&usb2_phy0 1>;
+			phy-names = "usb";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ohci1: usb@11c70000 {
+			compatible = "generic-ohci";
+			reg = <0 0x11c70000 0 0x100>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+			resets = <&phyrst 1>,
+				 <&cpg R9A07G044_USB_U2H1_HRESETN>;
+			phys = <&usb2_phy1 1>;
+			phy-names = "usb";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ehci0: usb@11c50100 {
+			compatible = "generic-ehci";
+			reg = <0 0x11c50100 0 0x100>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+			resets = <&phyrst 0>,
+				 <&cpg R9A07G044_USB_U2H0_HRESETN>;
+			phys = <&usb2_phy0 2>;
+			phy-names = "usb";
+			companion = <&ohci0>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ehci1: usb@11c70100 {
+			compatible = "generic-ehci";
+			reg = <0 0x11c70100 0 0x100>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+			resets = <&phyrst 1>,
+				 <&cpg R9A07G044_USB_U2H1_HRESETN>;
+			phys = <&usb2_phy1 2>;
+			phy-names = "usb";
+			companion = <&ohci1>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		usb2_phy0: usb-phy@11c50200 {
+			compatible = "renesas,usb2-phy-r9a07g044",
+				     "renesas,rzg2l-usb2-phy";
+			reg = <0 0x11c50200 0 0x700>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+			resets = <&phyrst 0>;
+			#phy-cells = <1>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		usb2_phy1: usb-phy@11c70200 {
+			compatible = "renesas,usb2-phy-r9a07g044",
+				     "renesas,rzg2l-usb2-phy";
+			reg = <0 0x11c70200 0 0x700>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+			resets = <&phyrst 1>;
+			#phy-cells = <1>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
 	};
 
 	timer {
-- 
2.17.1

[PATCH v6 3/3] arm64: dts: renesas: r9a07g044: Add USB2.0 device support

[Biju Das]

Add USB2.0 device support to RZ/G2L SoC DT.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v5->v6:
 * Added Rb tag from Geert.
v4->v5:
 * No change.
v3->v4:
 * No change.
 V3:
  * Updated reset entries.
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index de78c921af22..2f313c2a81c7 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -391,6 +391,25 @@
 			power-domains = <&cpg>;
 			status = "disabled";
 		};
+
+		hsusb: usb@11c60000 {
+			compatible = "renesas,usbhs-r9a07g044",
+				     "renesas,rza2-usbhs";
+			reg = <0 0x11c60000 0 0x10000>;
+			interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+				 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
+			resets = <&phyrst 0>,
+				 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
+			renesas,buswait = <7>;
+			phys = <&usb2_phy0 3>;
+			phy-names = "usb";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
 	};
 
 	timer {
-- 
2.17.1

Re: [PATCH v6 3/3] arm64: dts: renesas: r9a07g044: Add USB2.0 device support

[Sergei Shtylyov]

On 8/12/21 6:18 PM, Biju Das wrote:

> Add USB2.0 device support to RZ/G2L SoC DT.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[...]
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> index de78c921af22..2f313c2a81c7 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -391,6 +391,25 @@
>  			power-domains = <&cpg>;
>  			status = "disabled";
>  		};
> +
> +		hsusb: usb@11c60000 {
> +			compatible = "renesas,usbhs-r9a07g044",
> +				     "renesas,rza2-usbhs";
> +			reg = <0 0x11c60000 0 0x10000>;
> +			interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;

   Don't we need to specify "interrupt-names" when there a more than 1 interrupts?

> +			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
> +				 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;

   And "clock-names" too?

> +			resets = <&phyrst 0>,
> +				 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;

   And "reset-names"?

[...]

MBR, Sergei

RE: [PATCH v6 3/3] arm64: dts: renesas: r9a07g044: Add USB2.0 device support

[Biju Das]

Hi Sergei,

Thanks for the feedback.

> Subject: Re: [PATCH v6 3/3] arm64: dts: renesas: r9a07g044: Add USB2.0
> device support
> 
> On 8/12/21 6:18 PM, Biju Das wrote:
> 
> > Add USB2.0 device support to RZ/G2L SoC DT.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> [...]
> > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > index de78c921af22..2f313c2a81c7 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > @@ -391,6 +391,25 @@
> >  			power-domains = <&cpg>;
> >  			status = "disabled";
> >  		};
> > +
> > +		hsusb: usb@11c60000 {
> > +			compatible = "renesas,usbhs-r9a07g044",
> > +				     "renesas,rza2-usbhs";
> > +			reg = <0 0x11c60000 0 0x10000>;
> > +			interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
> > +				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> 
>    Don't we need to specify "interrupt-names" when there a more than 1
> interrupts?

This dtsi changes, as per binding documentation [1]. As you see, "interrupt-names" is optional.

[1] :- https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml?h=next-20210812

> 
> > +			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
> > +				 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
> 
>    And "clock-names" too?

Same here. It is optional.

> 
> > +			resets = <&phyrst 0>,
> > +				 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
> 
>    And "reset-names"?

Same here. It is optional.

Regards,
Biju
> 
> [...]
> 
> MBR, Sergei

RE: [PATCH v6 3/3] arm64: dts: renesas: r9a07g044: Add USB2.0 device support

[Biju Das]

Hi All,

> Subject: RE: [PATCH v6 3/3] arm64: dts: renesas: r9a07g044: Add USB2.0
> device support
> 
> Hi Sergei,
> 
> Thanks for the feedback.
> 
> > Subject: Re: [PATCH v6 3/3] arm64: dts: renesas: r9a07g044: Add USB2.0
> > device support
> >
> > On 8/12/21 6:18 PM, Biju Das wrote:
> >
> > > Add USB2.0 device support to RZ/G2L SoC DT.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > [...]
> > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > index de78c921af22..2f313c2a81c7 100644
> > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > @@ -391,6 +391,25 @@
> > >  			power-domains = <&cpg>;
> > >  			status = "disabled";
> > >  		};
> > > +
> > > +		hsusb: usb@11c60000 {
> > > +			compatible = "renesas,usbhs-r9a07g044",
> > > +				     "renesas,rza2-usbhs";
> > > +			reg = <0 0x11c60000 0 0x10000>;
> > > +			interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
> > > +				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> > > +				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> > > +				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> >
> >    Don't we need to specify "interrupt-names" when there a more than 1
> > interrupts?
> 
> This dtsi changes, as per binding documentation [1]. As you see,
> "interrupt-names" is optional.

For now I will go with current dt changes.

Later  I will create incremental patches for dt-binding with optional "interrupt-names",
"clock-names" and "reset names" for all the SoC's supported by this binding doc. 

After that, will send an incremental patch with adding optional properties in all SoC dtsi.

Does it make sense?

Regards,
Biju

> 
> [1] :- https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-
> next.git/tree/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml?h=n
> ext-20210812
> 
> >
> > > +			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
> > > +				 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
> >
> >    And "clock-names" too?
> 
> Same here. It is optional.
> 
> >
> > > +			resets = <&phyrst 0>,
> > > +				 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
> >
> >    And "reset-names"?
> 
> Same here. It is optional.
> 
> Regards,
> Biju
> >
> > [...]
> >
> > MBR, Sergei

Re: [PATCH v6 3/3] arm64: dts: renesas: r9a07g044: Add USB2.0 device support

[Sergey Shtylyov]

On 8/17/21 2:12 PM, Biju Das wrote:

[...]
>>>> Add USB2.0 device support to RZ/G2L SoC DT.
>>>>
>>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>>>> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>> [...]
>>>> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
>>> b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
>>>> index de78c921af22..2f313c2a81c7 100644
>>>> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
>>>> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
>>>> @@ -391,6 +391,25 @@
>>>>  			power-domains = <&cpg>;
>>>>  			status = "disabled";
>>>>  		};
>>>> +
>>>> +		hsusb: usb@11c60000 {
>>>> +			compatible = "renesas,usbhs-r9a07g044",
>>>> +				     "renesas,rza2-usbhs";
>>>> +			reg = <0 0x11c60000 0 0x10000>;
>>>> +			interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
>>>> +				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
>>>> +				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
>>>> +				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
>>>
>>>    Don't we need to specify "interrupt-names" when there a more than 1
>>> interrupts?
>>
>> This dtsi changes, as per binding documentation [1]. As you see,
>> "interrupt-names" is optional.
> 
> For now I will go with current dt changes.
> 
> Later  I will create incremental patches for dt-binding with optional "interrupt-names",
> "clock-names" and "reset names" for all the SoC's supported by this binding doc. 
> 
> After that, will send an incremental patch with adding optional properties in all SoC dtsi.
> 
> Does it make sense?

   I had the impression that the "*-names" prop was mandatory for a "*" prop having 2 values or mores.
If it's now allowed to be optional, don't bother with that at all.

> Regards,
> Biju


MBR, Sergei

Re: [PATCH v6 3/3] arm64: dts: renesas: r9a07g044: Add USB2.0 device support

[Geert Uytterhoeven]

Hi Sergey,

On Tue, Aug 17, 2021 at 6:41 PM Sergey Shtylyov <s.shtylyov@omp.ru> wrote:
> On 8/17/21 2:12 PM, Biju Das wrote:
> [...]
> >>>> Add USB2.0 device support to RZ/G2L SoC DT.
> >>>>
> >>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >>>> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >>> [...]
> >>>> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> >>> b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> >>>> index de78c921af22..2f313c2a81c7 100644
> >>>> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> >>>> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> >>>> @@ -391,6 +391,25 @@
> >>>>                    power-domains = <&cpg>;
> >>>>                    status = "disabled";
> >>>>            };
> >>>> +
> >>>> +          hsusb: usb@11c60000 {
> >>>> +                  compatible = "renesas,usbhs-r9a07g044",
> >>>> +                               "renesas,rza2-usbhs";
> >>>> +                  reg = <0 0x11c60000 0 0x10000>;
> >>>> +                  interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
> >>>> +                               <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> >>>> +                               <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> >>>> +                               <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> >>>
> >>>    Don't we need to specify "interrupt-names" when there a more than 1
> >>> interrupts?
> >>
> >> This dtsi changes, as per binding documentation [1]. As you see,
> >> "interrupt-names" is optional.
> >
> > For now I will go with current dt changes.
> >
> > Later  I will create incremental patches for dt-binding with optional "interrupt-names",
> > "clock-names" and "reset names" for all the SoC's supported by this binding doc.
> >
> > After that, will send an incremental patch with adding optional properties in all SoC dtsi.
> >
> > Does it make sense?
>
>    I had the impression that the "*-names" prop was mandatory for a "*" prop having 2 values or mores.
> If it's now allowed to be optional, don't bother with that at all.

There's a difference between "mandatory according to good DT
binding design" and "mandatory according to the actual json-schema
DT bindings".  For now the tools only enforce the latter...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v6 1/3] arm64: defconfig: Enable RZ/G2L USBPHY control driver

[Geert Uytterhoeven]

On Thu, Aug 12, 2021 at 5:18 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> RZ/G2L SoC supports USBPHY control,so enable it in ARM64 defconfig.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.16.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds