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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: RE: [PATCH v2 3/4] drivers: clk: renesas: rzg2l-cpg: Add support to handle coupled clocks
Date: Thu, 12 Aug 2021 06:59:50 +0000	[thread overview]
Message-ID: <OS0PR01MB5922E8535729D5AF997B33E986F99@OS0PR01MB5922.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <CAMuHMdUyiarunEWaQPyR+R+7RbMBXm-xaE1HpuyTwCcNymVS2g@mail.gmail.com>

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v2 3/4] drivers: clk: renesas: rzg2l-cpg: Add support
> to handle coupled clocks
> 
> Hi Biju,
> 
> On Tue, Jul 27, 2021 at 4:18 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > The AXI and CHI clocks use the same register bit for controlling clock
> > output. Add a new clock type for coupled clocks, which sets the
> > CPG_CLKON_ETH.CLK[01]_ON bit when at least one clock is enabled, and
> > clears the bit only when both clocks are disabled.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > @@ -333,12 +333,16 @@ rzg2l_cpg_register_core_clk(const struct
> cpg_core_clk *core,
> >   * @hw: handle between common and hardware-specific interfaces
> >   * @off: register offset
> >   * @bit: ON/MON bit
> > + * @is_coupled: flag to indicate coupled clock
> > + * @on_cnt: ON count for coupled clocks
> >   * @priv: CPG/MSTP private data
> >   */
> >  struct mstp_clock {
> >         struct clk_hw hw;
> >         u16 off;
> >         u8 bit;
> > +       bool is_coupled;
> > +       u8 on_cnt;
> 
> While u8 is probably sufficient, you may want to use unsigned int, as
> there will be a gap anyway due to alignment rules.
> 
> >         struct rzg2l_cpg_priv *priv;
> >  };
> >
> > @@ -392,11 +396,37 @@ static int rzg2l_mod_clock_endisable(struct
> > clk_hw *hw, bool enable)
> >
> >  static int rzg2l_mod_clock_enable(struct clk_hw *hw)  {
> > +       struct mstp_clock *clock = to_mod_clock(hw);
> > +       struct rzg2l_cpg_priv *priv = clock->priv;
> > +       unsigned long flags;
> > +
> > +       spin_lock_irqsave(&priv->rmw_lock, flags);
> > +       clock->on_cnt++;
> > +       if (clock->is_coupled && clock->on_cnt > 1) {
> > +               spin_unlock_irqrestore(&priv->rmw_lock, flags);
> > +               return 1;
> > +       }
> > +
> > +       spin_unlock_irqrestore(&priv->rmw_lock, flags);
> 
> I think you can avoid taking the spinlock and touching the counter if the
> is_coupled flag is not set.

OK.

> 
> > +
> >         return rzg2l_mod_clock_endisable(hw, true);  }
> 
> However, I'm wondering how this can work?
> 
>       DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
>                               0x57c, 0),
>       DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
>                               0x57c, 0),
> 
> This will create 2 independent clocks, each with their own mstp_clock
> structure that has the is_coupled flag set.  Hence each clock has its own
> counter. Shouldn't the counter be shared?
> Am I missing something?

Oops. You are correct. I need to add this counter to priv instead of mstp_clocks.

> 
> And what about rzg2l_mod_clock_is_enabled()?
> Shouldn't it reflect the soft state instead of the shared hardware state?

OK, will return Soft state for coupled clocks.

Cheers,
Biju

  reply	other threads:[~2021-08-12  6:59 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-27 14:17 [PATCH v2 0/4] Add GbEthernet Clock support Biju Das
2021-07-27 14:17 ` [PATCH v2 1/4] drivers: clk: renesas: rzg2l-cpg: Add support to handle MUX clocks Biju Das
2021-07-27 14:17 ` [PATCH v2 2/4] drivers: clk: renesas: r9a07g044-cpg: Add ethernet clock sources Biju Das
2021-07-27 14:17 ` [PATCH v2 3/4] drivers: clk: renesas: rzg2l-cpg: Add support to handle coupled clocks Biju Das
2021-08-11 10:18   ` Geert Uytterhoeven
2021-08-12  6:59     ` Biju Das [this message]
2021-08-12  7:54       ` Geert Uytterhoeven
2021-08-13 12:16         ` Biju Das
2021-08-13 12:46           ` Geert Uytterhoeven
2021-08-13 18:01             ` Biju Das
2021-07-27 14:17 ` [PATCH v2 4/4] drivers: clk: renesas: r9a07g044-cpg: Add GbEthernet clock/reset Biju Das

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