[PATCH rza_u-boot-2017.05 0/2] rza2mevb: Allow using Ethernet when SDRAM is enabled

[PATCH rza_u-boot-2017.05 0/2] rza2mevb: Allow using Ethernet when SDRAM is enabled

[Geert Uytterhoeven]

	Hi Chris,

To use the 64 MiB of SDRAM on the RZA2MEVB development board, SW6-4 must
be switched off, making the first Ethernet port unavailable.
Fortunately RZA2MEVB has two Ethernet ports, so this patch series makes
U-Boot fall back to using the second port instead.

Note that this does not apply to upstream U-Boot, as the sh_eth driver
has been reworked in upstream, and as upstream does not support RZA2MEVB
yet.

While this allows me to use TFTP, I still cannot boot my own non-XIP
Linux kernel (uImage with LOADADDR=0x0c008000), as it seems to crash in
the "blcs cache_on" in linux/arch/arm/boot/compressed/head.S.  A similar
kernel boots fine on RSK+RZA1.

Thanks for your comments!

Geert Uytterhoeven (2):
  net: sh_eth: Fix port offset on RZ/A2
  rza2mevb: Use second Ethernet port if first one is not available

 drivers/net/sh_eth.h       | 11 ++++++++---
 include/configs/rza2mevb.h |  4 ++++
 2 files changed, 12 insertions(+), 3 deletions(-)

-- 
2.17.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH rza_u-boot-2017.05 1/2] net: sh_eth: Fix port offset on RZ/A2

[Geert Uytterhoeven]

The sh_eth driver assumes a hardcoded offset of 0x800 between multiple
port instances, which is incorrect on RZ/A2.

Fix this by making the port offset configurable, depending on SoC type.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/net/sh_eth.h | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 906d93d8e7e0421f..d20abc7873e45850 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -366,8 +366,13 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #define BASE_IO_ADDR	0xE8203000
 #elif defined(CONFIG_R7S9210)
 #define SH_ETH_TYPE_RZ
-#define BASE_IO_ADDR	0xE8204000	/* EDMAC0 + ETHERC0 */
-//#define BASE_IO_ADDR	0xE8204200	/* EDMAC1 + ETHERC1 */
+#define BASE_IO_ADDR	0xE8204000
+#endif
+
+#if defined(CONFIG_R7S9210)
+#define PORT_OFFSET	0x200
+#else
+#define PORT_OFFSET	0x800
 #endif
 
 /*
@@ -674,7 +679,7 @@ static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
 #else
 #error
 #endif
-	return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
+	return BASE_IO_ADDR + reg_offset[enum_index] + PORT_OFFSET * eth->port;
 }
 
 static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
-- 
2.17.1

RE: [PATCH rza_u-boot-2017.05 1/2] net: sh_eth: Fix port offset on RZ/A2

[Chris Brandt]

Hi Geert,

Thank you!

Applied.

Chris


On Thu, Jul 04, 2019 1, Geert Uytterhoeven wrote:
> The sh_eth driver assumes a hardcoded offset of 0x800 between multiple
> port instances, which is incorrect on RZ/A2.
> 
> Fix this by making the port offset configurable, depending on SoC type.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/net/sh_eth.h | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
> index 906d93d8e7e0421f..d20abc7873e45850 100644
> --- a/drivers/net/sh_eth.h
> +++ b/drivers/net/sh_eth.h
> @@ -366,8 +366,13 @@ static const u16
> sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
>  #define BASE_IO_ADDR	0xE8203000
>  #elif defined(CONFIG_R7S9210)
>  #define SH_ETH_TYPE_RZ
> -#define BASE_IO_ADDR	0xE8204000	/* EDMAC0 + ETHERC0 */
> -//#define BASE_IO_ADDR	0xE8204200	/* EDMAC1 + ETHERC1 */
> +#define BASE_IO_ADDR	0xE8204000
> +#endif
> +
> +#if defined(CONFIG_R7S9210)
> +#define PORT_OFFSET	0x200
> +#else
> +#define PORT_OFFSET	0x800
>  #endif
> 
>  /*
> @@ -674,7 +679,7 @@ static inline unsigned long sh_eth_reg_addr(struct
> sh_eth_dev *eth,
>  #else
>  #error
>  #endif
> -	return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
> +	return BASE_IO_ADDR + reg_offset[enum_index] + PORT_OFFSET * eth-
> >port;
>  }
> 
>  static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long
> data,
> --
> 2.17.1

[PATCH rza_u-boot-2017.05 2/2] rza2mevb: Use second Ethernet port if first one is not available

[Geert Uytterhoeven]

When SW6-4 is switched off, the first Ethernet port is not available,
and thus doesn't work.  Hence fall back to using the second port
instead.

This allows to use TFTP when SDRAM is enabled (RZA2M_ENABLE_SDRAM is
defined), and the serial console is moved to SCIF2.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 include/configs/rza2mevb.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/configs/rza2mevb.h b/include/configs/rza2mevb.h
index 7ac9b8f80e329288..a217d668eedae631 100644
--- a/include/configs/rza2mevb.h
+++ b/include/configs/rza2mevb.h
@@ -216,7 +216,11 @@
 /* Network interface */
 #if (SW6_4 == SW_ON) || (SW6_5 == SW_ON)
 #define CONFIG_SH_ETHER
+#if (SW6_4 == SW_ON)
 #define CONFIG_SH_ETHER_USE_PORT	0
+#else
+#define CONFIG_SH_ETHER_USE_PORT	1
+#endif
 #define CONFIG_SH_ETHER_PHY_ADDR	0
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 #define CONFIG_PHYLIB
-- 
2.17.1

RE: [PATCH rza_u-boot-2017.05 2/2] rza2mevb: Use second Ethernet port if first one is not available

[Chris Brandt]

Hi Geert,

Thank you!

Applied.

Chris

On Thu, Jul 04, 2019 1, Geert Uytterhoeven wrote:
> When SW6-4 is switched off, the first Ethernet port is not available,
> and thus doesn't work.  Hence fall back to using the second port
> instead.
> 
> This allows to use TFTP when SDRAM is enabled (RZA2M_ENABLE_SDRAM is
> defined), and the serial console is moved to SCIF2.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  include/configs/rza2mevb.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/include/configs/rza2mevb.h b/include/configs/rza2mevb.h
> index 7ac9b8f80e329288..a217d668eedae631 100644
> --- a/include/configs/rza2mevb.h
> +++ b/include/configs/rza2mevb.h
> @@ -216,7 +216,11 @@
>  /* Network interface */
>  #if (SW6_4 == SW_ON) || (SW6_5 == SW_ON)
>  #define CONFIG_SH_ETHER
> +#if (SW6_4 == SW_ON)
>  #define CONFIG_SH_ETHER_USE_PORT	0
> +#else
> +#define CONFIG_SH_ETHER_USE_PORT	1
> +#endif
>  #define CONFIG_SH_ETHER_PHY_ADDR	0
>  #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
>  #define CONFIG_PHYLIB
> --
> 2.17.1

RE: [PATCH rza_u-boot-2017.05 0/2] rza2mevb: Allow using Ethernet when SDRAM is enabled

[Chris Brandt]

Hi Geert,

Sorry for the delay while I was on vacation.

On Thu, Jul 04, 2019 1, Geert Uytterhoeven wrote:
> To use the 64 MiB of SDRAM on the RZA2MEVB development board, SW6-4 must
> be switched off, making the first Ethernet port unavailable.
> Fortunately RZA2MEVB has two Ethernet ports, so this patch series makes
> U-Boot fall back to using the second port instead.

Thank you for the patches!


> While this allows me to use TFTP, I still cannot boot my own non-XIP
> Linux kernel (uImage with LOADADDR=0x0c008000), as it seems to crash in
> the "blcs cache_on" in linux/arch/arm/boot/compressed/head.S.  A similar
> kernel boots fine on RSK+RZA1.

Maybe it is because of the fact that for RZ/A1, both the RSK and GENMAI 
boards are using CS2 so the SDRAM was located at address 0x0800000.
But the RZ/A2M EVB has SDRAM on CS3, so the address is 0x0C000000.


Here was a patch that I had to do back in our linux-3.14 kernel for 
those that were using CS3.
https://github.com/renesas-rz/rza_linux-3.14/commit/86ee3b7bc1f5


It looks like the current kernel has the same mask, and will need the
same fix.
https://github.com/renesas-rz/rza_linux-4.19/blob/master/arch/arm/boot/compressed/head.S#L207


Does that fix your issue?

Chris

Re: [PATCH rza_u-boot-2017.05 0/2] rza2mevb: Allow using Ethernet when SDRAM is enabled

[Geert Uytterhoeven]

Hi Chris,

On Wed, Jul 10, 2019 at 9:16 PM Chris Brandt <Chris.Brandt@renesas.com> wrote:
> On Thu, Jul 04, 2019 1, Geert Uytterhoeven wrote:
> > While this allows me to use TFTP, I still cannot boot my own non-XIP
> > Linux kernel (uImage with LOADADDR=0x0c008000), as it seems to crash in
> > the "blcs cache_on" in linux/arch/arm/boot/compressed/head.S.  A similar
> > kernel boots fine on RSK+RZA1.
>
> Maybe it is because of the fact that for RZ/A1, both the RSK and GENMAI
> boards are using CS2 so the SDRAM was located at address 0x0800000.
> But the RZ/A2M EVB has SDRAM on CS3, so the address is 0x0C000000.
>
>
> Here was a patch that I had to do back in our linux-3.14 kernel for
> those that were using CS3.
> https://github.com/renesas-rz/rza_linux-3.14/commit/86ee3b7bc1f5
>
>
> It looks like the current kernel has the same mask, and will need the
> same fix.
> https://github.com/renesas-rz/rza_linux-4.19/blob/master/arch/arm/boot/compressed/head.S#L207
>
>
> Does that fix your issue?

Thanks, that improves the situation. Now it continues to:

    Uncompressing Linux... done, booting the kernel.

and then it hangs.


Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH rza_u-boot-2017.05 0/2] rza2mevb: Allow using Ethernet when SDRAM is enabled

[Chris Brandt]

Hi Geert,

On Thu, Jul 11, 2019, Geert Uytterhoeven wrote:
> > Does that fix your issue?
> 
> Thanks, that improves the situation. Now it continues to:
> 
>     Uncompressing Linux... done, booting the kernel.
> 
> and then it hangs.

OK.
I will try it myself today and will see if I can get it to boot.

Chris