* [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100)
@ 2020-02-03 19:34 Sergei Shtylyov
2020-02-03 19:40 ` [PATCH RFT 1/5] sh_eth: check sh_eth_cpu_data::no_tx_cntrs when dumping registers Sergei Shtylyov
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Sergei Shtylyov @ 2020-02-03 19:34 UTC (permalink / raw)
To: David S. Miller, linux-renesas-soc; +Cc: Chris Brandt
Hello!
Here's a set of 5 patches against DaveM's 'net-next.git' repo.
I changed my mind about the RZ/A1 SoC needing its own register map --
now that we don't depend on the register map array in order to
determine whether a given register exists any more, we can add
a new flag to determine if the GECMR exists (this register is
present only on true GEther chips, not RZ/A1). We also need to
add the sh_eth_cpu_data::* flag checks where they were missing
so far: in the ethtool API for the register dump. I'd appreciate
if Chris Brandt could sanity-test this patch set as he seem to
still have the RZ/A1 hardware...
I'm not posting the patch set to the 'netdev' ML as the 'net-next' patches are unacceptable during the merge window there...
[1/5] sh_eth: check sh_eth_cpu_data::no_tx_cntrs when dumping registers
[2/5] sh_eth: check sh_eth_cpu_data::cexcr when dumping registers
[3/5] sh_eth: check sh_eth_cpu_data::no_xdfar when dumping registers
[4/5] sh_eth: add sh_eth_cpu_data::gecmr flag
[5/5] sh_eth: use Gigabit register map for R7S72100
MBR, Sergei
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH RFT 1/5] sh_eth: check sh_eth_cpu_data::no_tx_cntrs when dumping registers
2020-02-03 19:34 [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100) Sergei Shtylyov
@ 2020-02-03 19:40 ` Sergei Shtylyov
2020-02-03 19:42 ` [PATCH RFT 2/5] sh_eth: check sh_eth_cpu_data::cexcr " Sergei Shtylyov
` (5 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Sergei Shtylyov @ 2020-02-03 19:40 UTC (permalink / raw)
To: David S. Miller, linux-renesas-soc; +Cc: Chris Brandt
When adding the sh_eth_cpu_data::no_tx_cntrs flag I forgot to add the
flag check to __sh_eth_get_regs(), causing the non-existing TX counter
registers to be considered for dumping on the R7S72100 SoC (the register
offset sanity check has the final say here)...
Fixes: ce9134dff6d9 ("sh_eth: add sh_eth_cpu_data::no_tx_cntrs flag")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
drivers/net/ethernet/renesas/sh_eth.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
===================================================================
--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net-next/drivers/net/ethernet/renesas/sh_eth.c
@@ -2184,10 +2184,12 @@ static size_t __sh_eth_get_regs(struct n
add_reg(BCULR);
add_reg(MAHR);
add_reg(MALR);
- add_reg(TROCR);
- add_reg(CDCR);
- add_reg(LCCR);
- add_reg(CNDCR);
+ if (!cd->no_tx_cntrs) {
+ add_reg(TROCR);
+ add_reg(CDCR);
+ add_reg(LCCR);
+ add_reg(CNDCR);
+ }
add_reg(CEFCR);
add_reg(FRECR);
add_reg(TSFRCR);
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH RFT 2/5] sh_eth: check sh_eth_cpu_data::cexcr when dumping registers
2020-02-03 19:34 [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100) Sergei Shtylyov
2020-02-03 19:40 ` [PATCH RFT 1/5] sh_eth: check sh_eth_cpu_data::no_tx_cntrs when dumping registers Sergei Shtylyov
@ 2020-02-03 19:42 ` Sergei Shtylyov
2020-02-03 19:44 ` [PATCH RFT 3/5] sh_eth: check sh_eth_cpu_data::no_xdfar " Sergei Shtylyov
` (4 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Sergei Shtylyov @ 2020-02-03 19:42 UTC (permalink / raw)
To: David S. Miller, linux-renesas-soc; +Cc: Chris Brandt
When adding the sh_eth_cpu_data::cexcr flag I forgot to add the flag
check to __sh_eth_get_regs(), causing the non-existing RX packet counter
registers to be considered for dumping on the R7S72100 SoC (the register
offset sanity check has the final say here)...
Fixes: 4c1d45850d5 ("sh_eth: add sh_eth_cpu_data::cexcr flag")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
drivers/net/ethernet/renesas/sh_eth.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
===================================================================
--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net-next/drivers/net/ethernet/renesas/sh_eth.c
@@ -2194,8 +2194,10 @@ static size_t __sh_eth_get_regs(struct n
add_reg(FRECR);
add_reg(TSFRCR);
add_reg(TLFRCR);
- add_reg(CERCR);
- add_reg(CEECR);
+ if (cd->cexcr) {
+ add_reg(CERCR);
+ add_reg(CEECR);
+ }
add_reg(MAFCR);
if (cd->rtrate)
add_reg(RTRATE);
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH RFT 3/5] sh_eth: check sh_eth_cpu_data::no_xdfar when dumping registers
2020-02-03 19:34 [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100) Sergei Shtylyov
2020-02-03 19:40 ` [PATCH RFT 1/5] sh_eth: check sh_eth_cpu_data::no_tx_cntrs when dumping registers Sergei Shtylyov
2020-02-03 19:42 ` [PATCH RFT 2/5] sh_eth: check sh_eth_cpu_data::cexcr " Sergei Shtylyov
@ 2020-02-03 19:44 ` Sergei Shtylyov
2020-02-03 19:49 ` [PATCH RFT 4/5] sh_eth: add sh_eth_cpu_data::gecmr flag Sergei Shtylyov
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Sergei Shtylyov @ 2020-02-03 19:44 UTC (permalink / raw)
To: David S. Miller, linux-renesas-soc; +Cc: Chris Brandt
When adding the sh_eth_cpu_data::no_xdfar flag I forgot to add the flag
check to __sh_eth_get_regs(), causing the non-existing RDFAR/TDFAR to be
considered for dumping on the R-Car gen1/2 SoCs (the register offset check
has the final say here)...
Fixes: 4c1d45850d5 ("sh_eth: add sh_eth_cpu_data::cexcr flag")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
drivers/net/ethernet/renesas/sh_eth.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
===================================================================
--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net-next/drivers/net/ethernet/renesas/sh_eth.c
@@ -2140,11 +2140,13 @@ static size_t __sh_eth_get_regs(struct n
add_reg(EESR);
add_reg(EESIPR);
add_reg(TDLAR);
- add_reg(TDFAR);
+ if (!cd->no_xdfar)
+ add_reg(TDFAR);
add_reg(TDFXR);
add_reg(TDFFR);
add_reg(RDLAR);
- add_reg(RDFAR);
+ if (!cd->no_xdfar)
+ add_reg(RDFAR);
add_reg(RDFXR);
add_reg(RDFFR);
add_reg(TRSCER);
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH RFT 4/5] sh_eth: add sh_eth_cpu_data::gecmr flag
2020-02-03 19:34 [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100) Sergei Shtylyov
` (2 preceding siblings ...)
2020-02-03 19:44 ` [PATCH RFT 3/5] sh_eth: check sh_eth_cpu_data::no_xdfar " Sergei Shtylyov
@ 2020-02-03 19:49 ` Sergei Shtylyov
2020-02-03 19:51 ` [PATCH RFT 5/5] sh_eth: use Gigabit register map for R7S72100 Sergei Shtylyov
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Sergei Shtylyov @ 2020-02-03 19:49 UTC (permalink / raw)
To: David S. Miller, linux-renesas-soc; +Cc: Chris Brandt
Not all Ether controllers having the Gigabit register layout have GECMR --
RZ/A1 (AKA R7S72100) actually has the same layout but no Gigabit speed
support and hence no GECMR. In the past, the new register map table was
added for this SoC, now I think we should have used the existing Gigabit
table with the differences (such as GECMR) covered by the mere flags in
the 'struct sh_eth_cpu_data'. Add such flag for GECMR -- and then we can
get rid of the R7S72100 specific layout in the next patch...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
drivers/net/ethernet/renesas/sh_eth.c | 14 +++++++++++++-
drivers/net/ethernet/renesas/sh_eth.h | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
===================================================================
--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net-next/drivers/net/ethernet/renesas/sh_eth.c
@@ -569,6 +569,9 @@ static void sh_eth_set_rate_gether(struc
{
struct sh_eth_private *mdp = netdev_priv(ndev);
+ if (WARN_ON(!mdp->cd->gecmr))
+ return;
+
switch (mdp->speed) {
case 10: /* 10BASE */
sh_eth_write(ndev, GECMR_10, GECMR);
@@ -663,6 +666,7 @@ static struct sh_eth_cpu_data r8a7740_da
.apr = 1,
.mpr = 1,
.tpauser = 1,
+ .gecmr = 1,
.bculr = 1,
.hw_swap = 1,
.rpadir = 1,
@@ -788,6 +792,7 @@ static struct sh_eth_cpu_data r8a77980_d
.apr = 1,
.mpr = 1,
.tpauser = 1,
+ .gecmr = 1,
.bculr = 1,
.hw_swap = 1,
.nbst = 1,
@@ -957,6 +962,9 @@ static void sh_eth_set_rate_giga(struct
{
struct sh_eth_private *mdp = netdev_priv(ndev);
+ if (WARN_ON(!mdp->cd->gecmr))
+ return;
+
switch (mdp->speed) {
case 10: /* 10BASE */
sh_eth_write(ndev, 0x00000000, GECMR);
@@ -1002,6 +1010,7 @@ static struct sh_eth_cpu_data sh7757_dat
.apr = 1,
.mpr = 1,
.tpauser = 1,
+ .gecmr = 1,
.bculr = 1,
.hw_swap = 1,
.rpadir = 1,
@@ -1042,6 +1051,7 @@ static struct sh_eth_cpu_data sh7734_dat
.apr = 1,
.mpr = 1,
.tpauser = 1,
+ .gecmr = 1,
.bculr = 1,
.hw_swap = 1,
.no_trimd = 1,
@@ -1083,6 +1093,7 @@ static struct sh_eth_cpu_data sh7763_dat
.apr = 1,
.mpr = 1,
.tpauser = 1,
+ .gecmr = 1,
.bculr = 1,
.hw_swap = 1,
.no_trimd = 1,
@@ -2181,7 +2192,8 @@ static size_t __sh_eth_get_regs(struct n
if (cd->tpauser)
add_reg(TPAUSER);
add_reg(TPAUSECR);
- add_reg(GECMR);
+ if (cd->gecmr)
+ add_reg(GECMR);
if (cd->bculr)
add_reg(BCULR);
add_reg(MAHR);
Index: net-next/drivers/net/ethernet/renesas/sh_eth.h
===================================================================
--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.h
+++ net-next/drivers/net/ethernet/renesas/sh_eth.h
@@ -490,6 +490,7 @@ struct sh_eth_cpu_data {
unsigned apr:1; /* EtherC has APR */
unsigned mpr:1; /* EtherC has MPR */
unsigned tpauser:1; /* EtherC has TPAUSER */
+ unsigned gecmr:1; /* EtherC has GECMR */
unsigned bculr:1; /* EtherC has BCULR */
unsigned tsu:1; /* EtherC has TSU */
unsigned hw_swap:1; /* E-DMAC has DE bit in EDMR */
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH RFT 5/5] sh_eth: use Gigabit register map for R7S72100
2020-02-03 19:34 [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100) Sergei Shtylyov
` (3 preceding siblings ...)
2020-02-03 19:49 ` [PATCH RFT 4/5] sh_eth: add sh_eth_cpu_data::gecmr flag Sergei Shtylyov
@ 2020-02-03 19:51 ` Sergei Shtylyov
2020-02-03 20:01 ` Sergei Shtylyov
2020-02-04 3:35 ` [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100) Chris Brandt
2020-02-07 15:25 ` Chris Brandt
6 siblings, 1 reply; 11+ messages in thread
From: Sergei Shtylyov @ 2020-02-03 19:51 UTC (permalink / raw)
To: David S. Miller, linux-renesas-soc; +Cc: Chris Brandt
The register maps for the Gigabit controllers and the Ether one used on
RZ/A1 (AKA R7S72100) are identical except for GECMR which is only present
on the true GEther controllers. We no longer use the register map arrays
to determine if a given register exists, and have added the GECMR flag to
the 'struct sh_eth_cpu_data' in the previous patch, so we're ready to drop
the R7S72100 specific register map -- this saves 216 bytes of object code
(AArch gcc 4.8.5).
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
drivers/net/ethernet/renesas/sh_eth.c | 68 ----------------------------------
drivers/net/ethernet/renesas/sh_eth.h | 1
2 files changed, 1 insertion(+), 68 deletions(-)
Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
===================================================================
--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net-next/drivers/net/ethernet/renesas/sh_eth.c
@@ -142,69 +142,6 @@ static const u16 sh_eth_offset_gigabit[S
[FWALCR1] = 0x00b4,
};
-static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
- SH_ETH_OFFSET_DEFAULTS,
-
- [EDSR] = 0x0000,
- [EDMR] = 0x0400,
- [EDTRR] = 0x0408,
- [EDRRR] = 0x0410,
- [EESR] = 0x0428,
- [EESIPR] = 0x0430,
- [TDLAR] = 0x0010,
- [TDFAR] = 0x0014,
- [TDFXR] = 0x0018,
- [TDFFR] = 0x001c,
- [RDLAR] = 0x0030,
- [RDFAR] = 0x0034,
- [RDFXR] = 0x0038,
- [RDFFR] = 0x003c,
- [TRSCER] = 0x0438,
- [RMFCR] = 0x0440,
- [TFTR] = 0x0448,
- [FDR] = 0x0450,
- [RMCR] = 0x0458,
- [RPADIR] = 0x0460,
- [FCFTR] = 0x0468,
- [CSMR] = 0x04E4,
-
- [ECMR] = 0x0500,
- [RFLR] = 0x0508,
- [ECSR] = 0x0510,
- [ECSIPR] = 0x0518,
- [PIR] = 0x0520,
- [APR] = 0x0554,
- [MPR] = 0x0558,
- [PFTCR] = 0x055c,
- [PFRCR] = 0x0560,
- [TPAUSER] = 0x0564,
- [MAHR] = 0x05c0,
- [MALR] = 0x05c8,
- [CEFCR] = 0x0740,
- [FRECR] = 0x0748,
- [TSFRCR] = 0x0750,
- [TLFRCR] = 0x0758,
- [RFCR] = 0x0760,
- [MAFCR] = 0x0778,
-
- [ARSTR] = 0x0000,
- [TSU_CTRST] = 0x0004,
- [TSU_FWSLC] = 0x0038,
- [TSU_VTAG0] = 0x0058,
- [TSU_ADSBSY] = 0x0060,
- [TSU_TEN] = 0x0064,
- [TSU_POST1] = 0x0070,
- [TSU_POST2] = 0x0074,
- [TSU_POST3] = 0x0078,
- [TSU_POST4] = 0x007c,
- [TSU_ADRH0] = 0x0100,
-
- [TXNLCR0] = 0x0080,
- [TXALCR0] = 0x0084,
- [RXNLCR0] = 0x0088,
- [RXALCR0] = 0x008C,
-};
-
static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
SH_ETH_OFFSET_DEFAULTS,
@@ -593,7 +530,7 @@ static struct sh_eth_cpu_data r7s72100_d
.chip_reset = sh_eth_chip_reset,
.set_duplex = sh_eth_set_duplex,
- .register_type = SH_ETH_REG_FAST_RZ,
+ .register_type = SH_ETH_REG_GIGABIT,
.edtrr_trns = EDTRR_TRNS_GETHER,
.ecsr_value = ECSR_ICD,
@@ -3139,9 +3076,6 @@ static const u16 *sh_eth_get_register_of
case SH_ETH_REG_GIGABIT:
reg_offset = sh_eth_offset_gigabit;
break;
- case SH_ETH_REG_FAST_RZ:
- reg_offset = sh_eth_offset_fast_rz;
- break;
case SH_ETH_REG_FAST_RCAR:
reg_offset = sh_eth_offset_fast_rcar;
break;
Index: net-next/drivers/net/ethernet/renesas/sh_eth.h
===================================================================
--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.h
+++ net-next/drivers/net/ethernet/renesas/sh_eth.h
@@ -145,7 +145,6 @@ enum {
enum {
SH_ETH_REG_GIGABIT,
- SH_ETH_REG_FAST_RZ,
SH_ETH_REG_FAST_RCAR,
SH_ETH_REG_FAST_SH4,
SH_ETH_REG_FAST_SH3_SH2
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH RFT 5/5] sh_eth: use Gigabit register map for R7S72100
2020-02-03 19:51 ` [PATCH RFT 5/5] sh_eth: use Gigabit register map for R7S72100 Sergei Shtylyov
@ 2020-02-03 20:01 ` Sergei Shtylyov
0 siblings, 0 replies; 11+ messages in thread
From: Sergei Shtylyov @ 2020-02-03 20:01 UTC (permalink / raw)
To: David S. Miller, linux-renesas-soc; +Cc: Chris Brandt
On 02/03/2020 10:51 PM, Sergei Shtylyov wrote:
> The register maps for the Gigabit controllers and the Ether one used on
> RZ/A1 (AKA R7S72100) are identical except for GECMR which is only present
> on the true GEther controllers. We no longer use the register map arrays
> to determine if a given register exists, and have added the GECMR flag to
> the 'struct sh_eth_cpu_data' in the previous patch, so we're ready to drop
> the R7S72100 specific register map -- this saves 216 bytes of object code
> (AArch gcc 4.8.5).
Oops, it's called AArch64!
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100)
2020-02-03 19:34 [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100) Sergei Shtylyov
` (4 preceding siblings ...)
2020-02-03 19:51 ` [PATCH RFT 5/5] sh_eth: use Gigabit register map for R7S72100 Sergei Shtylyov
@ 2020-02-04 3:35 ` Chris Brandt
2020-02-07 15:25 ` Chris Brandt
6 siblings, 0 replies; 11+ messages in thread
From: Chris Brandt @ 2020-02-04 3:35 UTC (permalink / raw)
To: Sergei Shtylyov, David S. Miller, linux-renesas-soc
On Mon, Feb 3, 2020, Sergei Shtylyov wrote:
> I'd appreciate
> if Chris Brandt could sanity-test this patch set as he seem to
> still have the RZ/A1 hardware...
OK, I will give it a try this week.
Chris
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100)
2020-02-03 19:34 [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100) Sergei Shtylyov
` (5 preceding siblings ...)
2020-02-04 3:35 ` [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100) Chris Brandt
@ 2020-02-07 15:25 ` Chris Brandt
2020-02-07 15:40 ` Sergei Shtylyov
2020-02-07 15:51 ` Chris Brandt
6 siblings, 2 replies; 11+ messages in thread
From: Chris Brandt @ 2020-02-07 15:25 UTC (permalink / raw)
To: Sergei Shtylyov, David S. Miller, linux-renesas-soc
On Mon, Feb 3, 2020, Sergei Shtylyov wrote:
> so far: in the ethtool API for the register dump. I'd appreciate
> if Chris Brandt could sanity-test this patch set as he seem to
> still have the RZ/A1 hardware...
Works on a Renesas RZ/A1H RSK board.
Welcome to Buildroot
buildroot login: root
$ ifconfig eth0 up
[ 17.940062] Generic PHY e8203000.ethernet-ffffffff:00: attached PHY driver [Generic PHY] (mii_bus:phy_addr=e8203000.ethernet-ffffffff:00, irq=POLL)
[ 17.959339] sh-eth e8203000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off
[ 17.975071] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
$
$ udhcpc
udhcpc: started, v1.29.3
udhcpc: sending discover
udhcpc: sending select for 10.10.10.240
udhcpc: lease of 10.10.10.240 obtained, lease time 86400
deleting routers
adding dns 10.10.10.1
$
$
$ cd /tmp
$ wget www.google.com
Connecting to www.google.com (172.217.12.68:80)
index.html 100% |********************************| 11987 0:00:00 ETA
$
Chris
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100)
2020-02-07 15:25 ` Chris Brandt
@ 2020-02-07 15:40 ` Sergei Shtylyov
2020-02-07 15:51 ` Chris Brandt
1 sibling, 0 replies; 11+ messages in thread
From: Sergei Shtylyov @ 2020-02-07 15:40 UTC (permalink / raw)
To: Chris Brandt, David S. Miller, linux-renesas-soc
On 02/07/2020 06:25 PM, Chris Brandt wrote:
>> so far: in the ethtool API for the register dump. I'd appreciate
>> if Chris Brandt could sanity-test this patch set as he seem to
>> still have the RZ/A1 hardware...
> Works on a Renesas RZ/A1H RSK board.
Thank you!
Would you mind providing a formal Tested-by: tag?
MBR, Sergei
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100)
2020-02-07 15:25 ` Chris Brandt
2020-02-07 15:40 ` Sergei Shtylyov
@ 2020-02-07 15:51 ` Chris Brandt
1 sibling, 0 replies; 11+ messages in thread
From: Chris Brandt @ 2020-02-07 15:51 UTC (permalink / raw)
To: Sergei Shtylyov, David S. Miller, linux-renesas-soc
> On Fri, Feb 7, 2020, Chris Brandt wrote:
> On Mon, Feb 3, 2020, Sergei Shtylyov wrote:
> > so far: in the ethtool API for the register dump. I'd appreciate
> > if Chris Brandt could sanity-test this patch set as he seem to
> > still have the RZ/A1 hardware...
>
> Works on a Renesas RZ/A1H RSK board.
For the series:
Tested-by: Chris Brandt <chris.brandt@renesas.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-02-07 15:51 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-03 19:34 [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100) Sergei Shtylyov
2020-02-03 19:40 ` [PATCH RFT 1/5] sh_eth: check sh_eth_cpu_data::no_tx_cntrs when dumping registers Sergei Shtylyov
2020-02-03 19:42 ` [PATCH RFT 2/5] sh_eth: check sh_eth_cpu_data::cexcr " Sergei Shtylyov
2020-02-03 19:44 ` [PATCH RFT 3/5] sh_eth: check sh_eth_cpu_data::no_xdfar " Sergei Shtylyov
2020-02-03 19:49 ` [PATCH RFT 4/5] sh_eth: add sh_eth_cpu_data::gecmr flag Sergei Shtylyov
2020-02-03 19:51 ` [PATCH RFT 5/5] sh_eth: use Gigabit register map for R7S72100 Sergei Shtylyov
2020-02-03 20:01 ` Sergei Shtylyov
2020-02-04 3:35 ` [PATCH RFT 0/5] sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100) Chris Brandt
2020-02-07 15:25 ` Chris Brandt
2020-02-07 15:40 ` Sergei Shtylyov
2020-02-07 15:51 ` Chris Brandt
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