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Mon, 17 Dec 2018 11:24:39 +0000 From: Fabrizio Castro To: Simon Horman CC: Rob Herring , Geert Uytterhoeven , Mark Rutland , Magnus Damm , "linux-renesas-soc@vger.kernel.org" , "devicetree@vger.kernel.org" , Chris Paterson , Biju Das Subject: RE: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support Thread-Topic: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support Thread-Index: AQHUk5Cw21PJc0Kk+kO145apBL9P1aWB0amAgAD59QA= Date: Mon, 17 Dec 2018 11:24:39 +0000 Message-ID: References: <1544780260-27590-1-git-send-email-fabrizio.castro@bp.renesas.com> <1544780260-27590-3-git-send-email-fabrizio.castro@bp.renesas.com> <20181216201741.qqwmc44ogqifl52e@verge.net.au> In-Reply-To: <20181216201741.qqwmc44ogqifl52e@verge.net.au> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=fabrizio.castro@bp.renesas.com; x-originating-ip: [193.141.220.21] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;TY1PR01MB1706;20:MTcg7j36eG4NyC2T63ZJM+2jknJT+jm5JsMJ/QQ8xBeVV6Eh1KSQ0cVg1aWapr9dTakMtMj6sCvvur/hbHuHj+BJ9z8PImN1U2wTukOxY7pppoEFR4bKFL634RFUSZ+I3TLxUuoYQ5mASMzh5JhYLY3m3pgqYpeHiXBDKSu6vBc= x-ms-exchange-antispam-srfa-diagnostics: SOS;SOR; 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received-spf: None (protection.outlook.com: bp.renesas.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: CNM3Lgc3u6z2BKVwBF5iLo3t7aQU+RbbcDW0hwawj2680lJAAcGPael8BWlqH7NiduXuzDmtKEdZVqpy+h0NdONQEGqZu2R4kGQCytTg3Z5+kNedmZ0LTFjcLbHwGcSXa3o2nuQPkreSAN/sPdJq/SpMW1V0dCcg/DyXHrefDLIda/EcKtv8cPP4rtrdSwcnQiicymYoIQmKtyqfezuMQg8tWVtZdNf89wA3aOhvkBTOVnye0MMwc2fvOMkiWRlsdnL4r9C9bPuMoNy1RJfdlcb+136hDWVfJdcmwTj4lGTlBR11BKBB8ivRx0MlLhMb spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2d781dda-d1bb-418e-a823-08d664123bff X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Dec 2018 11:24:39.6942 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY1PR01MB1706 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hello Simon, > From: Simon Horman > Sent: 16 December 2018 20:18 > Subject: Re: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC= -DVFS support > > On Fri, Dec 14, 2018 at 09:37:25AM +0000, Fabrizio Castro wrote: > > Add the I2C[0-7] and IIC Bus Interface for DVFS (IIC for DVFS) > > devices nodes to the r8a774c0 device tree. > > > > Signed-off-by: Fabrizio Castro > > Thanks Fabrizo for this patch, it looks good to me with the exception of > one minor question I have below. > > > --- > > arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 143 ++++++++++++++++++++++= ++++++++ > > 1 file changed, 143 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boo= t/dts/renesas/r8a774c0.dtsi > > index 96a71e3..bf08aba 100644 > > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > > @@ -271,6 +271,149 @@ > > resets =3D <&cpg 407>; > > }; > > > > +i2c0: i2c@e6500000 { > > +#address-cells =3D <1>; > > +#size-cells =3D <0>; > > +compatible =3D "renesas,i2c-r8a774c0", > > + "renesas,rcar-gen3-i2c"; > > +reg =3D <0 0xe6500000 0 0x40>; > > +interrupts =3D ; > > +clocks =3D <&cpg CPG_MOD 931>; > > +power-domains =3D <&sysc R8A774C0_PD_ALWAYS_ON>; > > +resets =3D <&cpg 931>; > > +dmas =3D <&dmac1 0x91>, <&dmac1 0x90>, > > + <&dmac2 0x91>, <&dmac2 0x90>; > > +dma-names =3D "tx", "rx", "tx", "rx"; > > +i2c-scl-internal-delay-ns =3D <110>; > > +status =3D "disabled"; > > +}; > > + > > +i2c1: i2c@e6508000 { > > +#address-cells =3D <1>; > > +#size-cells =3D <0>; > > +compatible =3D "renesas,i2c-r8a774c0", > > + "renesas,rcar-gen3-i2c"; > > +reg =3D <0 0xe6508000 0 0x40>; > > +interrupts =3D ; > > +clocks =3D <&cpg CPG_MOD 930>; > > +power-domains =3D <&sysc R8A774C0_PD_ALWAYS_ON>; > > +resets =3D <&cpg 930>; > > +dmas =3D <&dmac1 0x93>, <&dmac1 0x92>, > > + <&dmac2 0x93>, <&dmac2 0x92>; > > +dma-names =3D "tx", "rx", "tx", "rx"; > > +i2c-scl-internal-delay-ns =3D <6>; > > +status =3D "disabled"; > > +}; > > + > > +i2c2: i2c@e6510000 { > > +#address-cells =3D <1>; > > +#size-cells =3D <0>; > > +compatible =3D "renesas,i2c-r8a774c0", > > + "renesas,rcar-gen3-i2c"; > > +reg =3D <0 0xe6510000 0 0x40>; > > +interrupts =3D ; > > +clocks =3D <&cpg CPG_MOD 929>; > > +power-domains =3D <&sysc R8A774C0_PD_ALWAYS_ON>; > > +resets =3D <&cpg 929>; > > +dmas =3D <&dmac1 0x95>, <&dmac1 0x94>, > > + <&dmac2 0x95>, <&dmac2 0x94>; > > +dma-names =3D "tx", "rx", "tx", "rx"; > > +i2c-scl-internal-delay-ns =3D <6>; > > +status =3D "disabled"; > > +}; > > + > > +i2c3: i2c@e66d0000 { > > +#address-cells =3D <1>; > > +#size-cells =3D <0>; > > +compatible =3D "renesas,i2c-r8a774c0", > > + "renesas,rcar-gen3-i2c"; > > +reg =3D <0 0xe66d0000 0 0x40>; > > +interrupts =3D ; > > +clocks =3D <&cpg CPG_MOD 928>; > > +power-domains =3D <&sysc R8A774C0_PD_ALWAYS_ON>; > > +resets =3D <&cpg 928>; > > +dmas =3D <&dmac0 0x97>, <&dmac0 0x96>; > > +dma-names =3D "tx", "rx"; > > +i2c-scl-internal-delay-ns =3D <110>; > > +status =3D "disabled"; > > +}; > > + > > +i2c4: i2c@e66d8000 { > > +#address-cells =3D <1>; > > +#size-cells =3D <0>; > > +compatible =3D "renesas,i2c-r8a774c0", > > + "renesas,rcar-gen3-i2c"; > > +reg =3D <0 0xe66d8000 0 0x40>; > > +interrupts =3D ; > > +clocks =3D <&cpg CPG_MOD 927>; > > +power-domains =3D <&sysc R8A774C0_PD_ALWAYS_ON>; > > +resets =3D <&cpg 927>; > > +dmas =3D <&dmac0 0x99>, <&dmac0 0x98>; > > +dma-names =3D "tx", "rx"; > > +i2c-scl-internal-delay-ns =3D <6>; > > +status =3D "disabled"; > > +}; > > + > > +i2c5: i2c@e66e0000 { > > +#address-cells =3D <1>; > > +#size-cells =3D <0>; > > +compatible =3D "renesas,i2c-r8a774c0", > > + "renesas,rcar-gen3-i2c"; > > +reg =3D <0 0xe66e0000 0 0x40>; > > +interrupts =3D ; > > +clocks =3D <&cpg CPG_MOD 919>; > > +power-domains =3D <&sysc R8A774C0_PD_ALWAYS_ON>; > > +resets =3D <&cpg 919>; > > +dmas =3D <&dmac0 0x9b>, <&dmac0 0x9a>; > > +dma-names =3D "tx", "rx"; > > +i2c-scl-internal-delay-ns =3D <6>; > > +status =3D "disabled"; > > +}; > > + > > +i2c6: i2c@e66e8000 { > > +#address-cells =3D <1>; > > +#size-cells =3D <0>; > > +compatible =3D "renesas,i2c-r8a774c0", > > + "renesas,rcar-gen3-i2c"; > > +reg =3D <0 0xe66e8000 0 0x40>; > > +interrupts =3D ; > > +clocks =3D <&cpg CPG_MOD 918>; > > +power-domains =3D <&sysc R8A774C0_PD_ALWAYS_ON>; > > +resets =3D <&cpg 918>; > > +dmas =3D <&dmac0 0x9d>, <&dmac0 0x9c>; > > +dma-names =3D "tx", "rx"; > > +i2c-scl-internal-delay-ns =3D <6>; > > +status =3D "disabled"; > > +}; > > + > > +i2c7: i2c@e6690000 { > > +#address-cells =3D <1>; > > +#size-cells =3D <0>; > > +compatible =3D "renesas,i2c-r8a774c0", > > + "renesas,rcar-gen3-i2c"; > > +reg =3D <0 0xe6690000 0 0x40>; > > +interrupts =3D ; > > +clocks =3D <&cpg CPG_MOD 1003>; > > +power-domains =3D <&sysc R8A774C0_PD_ALWAYS_ON>; > > +resets =3D <&cpg 1003>; > > +i2c-scl-internal-delay-ns =3D <6>; > > +status =3D "disabled"; > > +}; > > + > > +i2c_dvfs: i2c@e60b0000 { > > +#address-cells =3D <1>; > > +#size-cells =3D <0>; > > +compatible =3D "renesas,iic-r8a774c0"; > > +reg =3D <0 0xe60b0000 0 0x15>; > > My reading of the documentation is that 0x31 would be a more appropriate > size for the register window. Thank you for looking into this. RZ/G2 documentation about this seems a bit= incomplete at the moment, and we weren't too sure about what to do here. Our expectati= on is that the IP should be the same as the one found in R-Car E3, and we thought= they finally wanted to document some previously undocumented registers with the = RZ/G2 User's manual. We are waiting for some answers from Japan, and since the dr= iver doesn't support the "new" registers we thought there was no harm in using t= he same memory region used for R-Car E3. I can see the following options: * use 0x31 as you recommended * keep 0x15 and change it later on to the right figure once the driver actu= ally supports all of the documented registers (and maybe updated r8a77990.dtsi as well in cas= e the IP is the same?) * drop i2c_dvfs from this patch, and send it with a new patch once we get s= ome answers from Japan What's best option? Thanks, Fab > > > +interrupts =3D ; > > +clocks =3D <&cpg CPG_MOD 926>; > > +power-domains =3D <&sysc R8A774C0_PD_ALWAYS_ON>; > > +resets =3D <&cpg 926>; > > +dmas =3D <&dmac0 0x11>, <&dmac0 0x10>; > > +dma-names =3D "tx", "rx"; > > +status =3D "disabled"; > > +}; > > + > > hscif0: serial@e6540000 { > > compatible =3D "renesas,hscif-r8a774c0", > > "renesas,rcar-gen3-hscif", > > -- > > 2.7.4 > > [https://www2.renesas.eu/media/email/unicef.jpg] This Christmas, instead of sending out cards, Renesas Electronics Europe ha= ve decided to support Unicef with a donation. For further details click her= e to find out about the valuable work they do, hel= ping children all over the world. We would like to take this opportunity to wish you a Merry Christmas and a = prosperous New Year. Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, B= uckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered= No. 04586709.