[PATCH v2 0/6] clk: renesas: r8a77990: Add Z2 clock

[PATCH v2 0/6] clk: renesas: r8a77990: Add Z2 clock

[Simon Horman]

Hi,

this series adds the R-Car E3 (r8a77990) Z2 clock as a clock
with both a fixed and variable divisor with a parent of PLL0.

In order to do so this series:

1. Parameterise Z and Z2 clock fixed divisor in shared Gen-3 CPG
   dirver code to allow fixed divisors other than 2 - the E3 Z2
   clock has a fixed divisor of 4

2. Add a quirk to shared Gen-3 CPG to allow for an alternate location
   of the FRQCRC Z2 divider bits. This alternate location is used
   by the E3.

3. Support Z and Z2 clocks with high frequency parents.
   The parent of the E3 Z2 clock, PLL0, is 4.8GHz and thus
   when expressed in HZ must be treated as a 64bit value.

4. Actually add the E3 Z2 clock

As a follow-up, as per reading the documentation, the RZ/G2E (r8a7745)
Z2 is updated to be a variable rather than fixed clock.

Changes since v1
----------------
* Define Z2 as a variable rather than fixed clock


Testing Overview
----------------

This patchset has not been tested on RZ/G2E.

This patchset has been tested on Ebisu-4D/E3 with
"[PATCH/RFT] arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices"
applied on top of renesas-devel-20190128-v5.0-rc4. This allowed CPUFreq
to be successfully exercised, showing scaling of the Z2 clock as per the
results below.

This patchset was also tested for regressions Salvator-X/M3-W ES1.0.
As per the results below CPUFreq was used to show that with these
patches applied Z and Z2 clocks still scale as expected.


Patches List by Author
----------------------

Simon Horman (3):
  clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency
    parents
  [RFT] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock divider
  [RFT] clk: renesas: r8a7745: Implement Z2 as a variable clock

Takeshi Kihara (3):
  clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
  clk: renesas: rcar-gen3: Support r8a77990 Z2 clock divider
  clk: renesas: r8a77990: Add Z2 clock

 drivers/clk/renesas/r8a7745-cpg-mssr.c  |  2 +-
 drivers/clk/renesas/r8a774a1-cpg-mssr.c |  4 ++--
 drivers/clk/renesas/r8a7795-cpg-mssr.c  |  5 +++--
 drivers/clk/renesas/r8a7796-cpg-mssr.c  |  5 +++--
 drivers/clk/renesas/r8a77965-cpg-mssr.c |  2 +-
 drivers/clk/renesas/r8a77990-cpg-mssr.c |  1 +
 drivers/clk/renesas/rcar-gen3-cpg.c     | 38 +++++++++++++++++++++++++--------
 drivers/clk/renesas/rcar-gen3-cpg.h     |  4 ++++
 8 files changed, 44 insertions(+), 17 deletions(-)

-- 
2.11.0


Ebisu-4D/E3 Test Results
------------------------

# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
performance
# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
800000 1000000 1200000 
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z2/clk_rate:1200000000
# echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:975000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:975000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1000000
/sys/kernel/debug/clk/z2/clk_rate:975000000
# echo 800000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:787500
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:800000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:787500
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:800000
/sys/kernel/debug/clk/z2/clk_rate:787500000
# echo 1200000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z2/clk_rate:1200000000


Salvator-X/M3-W ES1 Test Results
--------------------------------

# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
performance
# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
500000 1000000 1500000 
# cat /sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies
800000 1000000 1200000 
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z/clk_rate /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1499999
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1500000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1499999
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1500000
/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu2/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu3/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu5/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z/clk_rate:1499999940
/sys/kernel/debug/clk/z2/clk_rate:1199999952
# echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z/clk_rate /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:984374
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:984374
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu2/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu3/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu5/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z/clk_rate:984374961
/sys/kernel/debug/clk/z2/clk_rate:1199999952
# echo 1000000 > /sys/devices/system/cpu/cpu2/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z/clk_rate /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:984374
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:984374
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_cur_freq:974999
/sys/devices/system/cpu/cpu2/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_cur_freq:974999
/sys/devices/system/cpu/cpu3/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq:974999
/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_cur_freq:974999
/sys/devices/system/cpu/cpu5/cpufreq/scaling_cur_freq:1000000
/sys/kernel/debug/clk/z/clk_rate:984374961
/sys/kernel/debug/clk/z2/clk_rate:974999961
# echo 500000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# echo 800000 > /sys/devices/system/cpu/cpu2/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z/clk_rate /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:468749
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:500000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:468749
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:500000
/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_cur_freq:787499
/sys/devices/system/cpu/cpu2/cpufreq/scaling_cur_freq:800000
/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_cur_freq:787499
/sys/devices/system/cpu/cpu3/cpufreq/scaling_cur_freq:800000
/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq:787499
/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq:800000
/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_cur_freq:787499
/sys/devices/system/cpu/cpu5/cpufreq/scaling_cur_freq:800000
/sys/kernel/debug/clk/z/clk_rate:468749981
/sys/kernel/debug/clk/z2/clk_rate:787499969
# echo 1500000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# echo 1200000 > /sys/devices/system/cpu/cpu2/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z/clk_rate /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1499999
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1500000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1499999
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1500000
/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu2/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu3/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_cur_freq:1199999
/sys/devices/system/cpu/cpu5/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z/clk_rate:1499999940
/sys/kernel/debug/clk/z2/clk_rate:1199999952

[PATCH v2 1/6] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor

[Simon Horman]

From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

Parameterise Z and Z2 clock fixed divisor to allow clocks with a fixed
divisor other than 2, the value used by all such clocks supported to date.

This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which has a fixed divisor of 4.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: squashed several patches; rewrote changelog; added r8a774a1 change]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/clk/renesas/r8a774a1-cpg-mssr.c |  4 ++--
 drivers/clk/renesas/r8a7795-cpg-mssr.c  |  5 +++--
 drivers/clk/renesas/r8a7796-cpg-mssr.c  |  5 +++--
 drivers/clk/renesas/r8a77965-cpg-mssr.c |  2 +-
 drivers/clk/renesas/rcar-gen3-cpg.c     | 23 ++++++++++++++---------
 drivers/clk/renesas/rcar-gen3-cpg.h     |  4 ++++
 6 files changed, 27 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 10e852518870..103253bee055 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -71,8 +71,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
 	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
 
 	/* Core Clock Outputs */
-	DEF_BASE("z",           R8A774A1_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),
-	DEF_BASE("z2",          R8A774A1_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),
+	DEF_GEN3_Z("z",		R8A774A1_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0, 2),
+	DEF_GEN3_Z("z2",	R8A774A1_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2, 2),
 	DEF_FIXED("ztr",        R8A774A1_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
 	DEF_FIXED("ztrd2",      R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
 	DEF_FIXED("zt",         R8A774A1_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 86842c9fd314..919861e6d428 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -3,6 +3,7 @@
  * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
  *
  * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2018 Renesas Electronics Corp.
  *
  * Based on clk-rcar-gen3.c
  *
@@ -73,8 +74,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
 	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
 
 	/* Core Clock Outputs */
-	DEF_BASE("z",           R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),
-	DEF_BASE("z2",          R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),
+	DEF_GEN3_Z("z",         R8A7795_CLK_Z,  CLK_TYPE_GEN3_Z,  CLK_PLL0, 2),
+	DEF_GEN3_Z("z2",        R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2),
 	DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
 	DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
 	DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 12c455859f2c..93983ec37e61 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -3,6 +3,7 @@
  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
  *
  * Copyright (C) 2016 Glider bvba
+ * Copyright (C) 2018 Renesas Electronics Corp.
  *
  * Based on r8a7795-cpg-mssr.c
  *
@@ -73,8 +74,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
 	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
 
 	/* Core Clock Outputs */
-	DEF_BASE("z",           R8A7796_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),
-	DEF_BASE("z2",          R8A7796_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),
+	DEF_GEN3_Z("z",         R8A7796_CLK_Z,  CLK_TYPE_GEN3_Z,  CLK_PLL0, 2),
+	DEF_GEN3_Z("z2",        R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2),
 	DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
 	DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
 	DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index eb1cca58a1e1..f8f73558c1ec 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -71,7 +71,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
 	DEF_GEN3_OSC(".r",	CLK_RINT,		CLK_EXTAL,	32),
 
 	/* Core Clock Outputs */
-	DEF_BASE("z",		R8A77965_CLK_Z,		CLK_TYPE_GEN3_Z, CLK_PLL0),
+	DEF_GEN3_Z("z",		R8A77965_CLK_Z,		CLK_TYPE_GEN3_Z,  CLK_PLL0, 2),
 	DEF_FIXED("ztr",	R8A77965_CLK_ZTR,	CLK_PLL1_DIV2,	6, 1),
 	DEF_FIXED("ztrd2",	R8A77965_CLK_ZTRD2,	CLK_PLL1_DIV2,	12, 1),
 	DEF_FIXED("zt",		R8A77965_CLK_ZT,	CLK_PLL1_DIV2,	4, 1),
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index be2ccbd6d623..d50dd53121bb 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -81,6 +81,7 @@ struct cpg_z_clk {
 	void __iomem *reg;
 	void __iomem *kick_reg;
 	unsigned long mask;
+	unsigned int fixed_div;
 };
 
 #define to_z_clk(_hw)	container_of(_hw, struct cpg_z_clk, hw)
@@ -95,17 +96,18 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
 	val = readl(zclk->reg) & zclk->mask;
 	mult = 32 - (val >> __ffs(zclk->mask));
 
-	/* Factor of 2 is for fixed divider */
-	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2);
+	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
+				     32 * zclk->fixed_div);
 }
 
 static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 				 unsigned long *parent_rate)
 {
-	/* Factor of 2 is for fixed divider */
-	unsigned long prate = *parent_rate / 2;
+	struct cpg_z_clk *zclk = to_z_clk(hw);
+	unsigned long prate;
 	unsigned int mult;
 
+	prate = *parent_rate / zclk->fixed_div;;
 	mult = div_u64(rate * 32ULL, prate);
 	mult = clamp(mult, 1U, 32U);
 
@@ -120,8 +122,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned int i;
 	u32 val, kick;
 
-	/* Factor of 2 is for fixed divider */
-	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);
+	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * zclk->fixed_div,
+				     parent_rate);
 	mult = clamp(mult, 1U, 32U);
 
 	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
@@ -167,7 +169,8 @@ static const struct clk_ops cpg_z_clk_ops = {
 static struct clk * __init cpg_z_clk_register(const char *name,
 					      const char *parent_name,
 					      void __iomem *reg,
-					      unsigned long mask)
+					      unsigned long mask,
+					      unsigned int div)
 {
 	struct clk_init_data init;
 	struct cpg_z_clk *zclk;
@@ -187,6 +190,7 @@ static struct clk * __init cpg_z_clk_register(const char *name,
 	zclk->kick_reg = reg + CPG_FRQCRB;
 	zclk->hw.init = &init;
 	zclk->mask = mask;
+	zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
 
 	clk = clk_register(NULL, &zclk->hw);
 	if (IS_ERR(clk))
@@ -565,11 +569,12 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
 
 	case CLK_TYPE_GEN3_Z:
 		return cpg_z_clk_register(core->name, __clk_get_name(parent),
-					  base, CPG_FRQCRC_ZFC_MASK);
+					  base, CPG_FRQCRC_ZFC_MASK, core->div);
 
 	case CLK_TYPE_GEN3_Z2:
 		return cpg_z_clk_register(core->name, __clk_get_name(parent),
-					  base, CPG_FRQCRC_Z2FC_MASK);
+					  base, CPG_FRQCRC_Z2FC_MASK,
+					  core->div);
 
 	case CLK_TYPE_GEN3_OSC:
 		/*
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index f4fb6cf16688..60038e245e8b 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -3,6 +3,7 @@
  * R-Car Gen3 Clock Pulse Generator
  *
  * Copyright (C) 2015-2018 Glider bvba
+ * Copyright (C) 2018 Renesas Electronics Corp.
  *
  */
 
@@ -48,6 +49,9 @@ enum rcar_gen3_clk_types {
 	DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL,	\
 		 (_parent0) << 16 | (_parent1),	.div = (_div0) << 16 | (_div1))
 
+#define DEF_GEN3_Z(_name, _id, _type, _parent, _div)	\
+	DEF_BASE(_name, _id, _type, _parent, .div = _div)
+
 struct rcar_gen3_cpg_pll_config {
 	u8 extal_div;
 	u8 pll1_mult;
-- 
2.11.0

[PATCH v2 2/6] clk: renesas: rcar-gen3: Support r8a77990 Z2 clock divider

[Simon Horman]

From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

Add support for the Z2 clock divider for the R-Car E3 (r8a77990) SoC.
On this SoC the Z2 clock divider bits of the FRQCRC register are found at
bit[12:8] rather than the more common location bit[4:0].

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: reworked changelog]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/clk/renesas/rcar-gen3-cpg.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index d50dd53121bb..db3b2efb40e9 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -74,6 +74,7 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
 #define CPG_FRQCRB_KICK			BIT(31)
 #define CPG_FRQCRC			0x000000e0
 #define CPG_FRQCRC_ZFC_MASK		GENMASK(12, 8)
+#define CPG_FRQCRC_Z2FC_SFT_8_MASK	GENMASK(12, 8)
 #define CPG_FRQCRC_Z2FC_MASK		GENMASK(4, 0)
 
 struct cpg_z_clk {
@@ -365,6 +366,7 @@ static u32 cpg_quirks __initdata;
 #define PLL_ERRATA	BIT(0)		/* Missing PLL0/2/4 post-divider */
 #define RCKCR_CKSEL	BIT(1)		/* Manual RCLK parent selection */
 #define SD_SKIP_FIRST	BIT(2)		/* Skip first clock in SD table */
+#define Z2FC_BIT_MASK_SFT_8	BIT(3)	/* Use Z2FC bit mask range to [12:8] */
 
 static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
 	void __iomem *base, const char *parent_name,
@@ -445,6 +447,10 @@ static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
 		.soc_id = "r8a7796", .revision = "ES1.1",
 		.data = (void *)SD_SKIP_FIRST,
 	},
+	{
+		.soc_id = "r8a77990",
+		.data = (void *)Z2FC_BIT_MASK_SFT_8,
+	},
 	{ /* sentinel */ }
 };
 
@@ -572,6 +578,12 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
 					  base, CPG_FRQCRC_ZFC_MASK, core->div);
 
 	case CLK_TYPE_GEN3_Z2:
+		if (cpg_quirks & Z2FC_BIT_MASK_SFT_8)
+			return cpg_z_clk_register(core->name,
+						  __clk_get_name(parent), base,
+						  CPG_FRQCRC_Z2FC_SFT_8_MASK,
+						  core->div);
+
 		return cpg_z_clk_register(core->name, __clk_get_name(parent),
 					  base, CPG_FRQCRC_Z2FC_MASK,
 					  core->div);
-- 
2.11.0

[PATCH v2 3/6] clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents

[Simon Horman]

Support Z and Z2 clocks with parent frequencies greater than
UINT32_MAX Hz (~4.29GHz).

The DIV_ROUND_CLOSEST_ULL() macro accepts a 64bit numerator and 32bit
denominator. This leads to truncation of the numerator, which is the Z or
Z2 parent clock frequency in HZ, on platforms where frequency of that clock
is greater than UINT32_MAX Hz.

To resolve this problem the DIV_ROUND_CLOSEST() macro, which accepts the
prevailing types of the numerator and denominator, is used. In this case
the type of the numerator is unsigned long long (64 bit) and the type of
the denominator is unsigned long (64bit on 64bit platforms and 32bit on
32bit platforms). This allows parents whose frequency is greater than
UINT32_MAX Hz on 64bit platforms.

This appears to be sufficient as this driver is only intended for use
on 64bit systems. And in particular, the motivation for this change is
to allow a 4.8GHz clock on the R-Car Gen3 E3 (r8a77990) SoC which is
a 64bit platform.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/clk/renesas/rcar-gen3-cpg.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index db3b2efb40e9..d21fdeb520e1 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -123,8 +123,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned int i;
 	u32 val, kick;
 
-	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * zclk->fixed_div,
-				     parent_rate);
+	mult = DIV_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, parent_rate);
 	mult = clamp(mult, 1U, 32U);
 
 	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
-- 
2.11.0

[PATCH v2 4/6] clk: renesas: r8a77990: Add Z2 clock

[Simon Horman]

From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

Adds support for R-Car E3 (r8a77990) Z2 clock.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: reworked changelog]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 9a278c75c918..05dc28e4ec5f 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
 	/* Core Clock Outputs */
 	DEF_FIXED("za2",       R8A77990_CLK_ZA2,   CLK_PLL0D24,    1, 1),
 	DEF_FIXED("za8",       R8A77990_CLK_ZA8,   CLK_PLL0D8,     1, 1),
+	DEF_GEN3_Z("z2",       R8A77990_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL0, 4),
 	DEF_FIXED("ztr",       R8A77990_CLK_ZTR,   CLK_PLL1,       6, 1),
 	DEF_FIXED("zt",        R8A77990_CLK_ZT,    CLK_PLL1,       4, 1),
 	DEF_FIXED("zx",        R8A77990_CLK_ZX,    CLK_PLL1,       3, 1),
-- 
2.11.0

[PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock divider

[Simon Horman]

On the RZ/G2E (r8a7745) SoC the Z2FC bits of the RFQCRC register,
which control the frequency division ratio for the Z2φ clock are
located at bit[12:8] rather than the more common location bit[4:0].

This change is made with reference to the User's Manual v0.61.

Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index d21fdeb520e1..dfd2b9caeaf5 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -450,6 +450,10 @@ static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
 		.soc_id = "r8a77990",
 		.data = (void *)Z2FC_BIT_MASK_SFT_8,
 	},
+	{
+		.soc_id = "r8a7745",
+		.data = (void *)Z2FC_BIT_MASK_SFT_8,
+	},
 	{ /* sentinel */ }
 };
 
-- 
2.11.0

[PATCH/RFT v2 6/6] clk: renesas: r8a7745: Implement Z2 as a variable clock

[Simon Horman]

On the RZ/G2E (r8a7745) SoC the Z2 clock is not a fixed clock.
Rather it is a clock with:

* A parent of CLK_PLL0 running at 4.8GHz
* A fixed divider of 4
* A variable divider controlled by the Z2FC bits of the RFQCRC register

This can be described using the DEF_GEN3_Z with a clock type of
CLK_TYPE_GEN3_Z2.

This change is made with reference to the User's Manual v0.61.

Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 493874e5ebee..f2ea72d9d663 100644
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -53,7 +53,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
 	DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,	CLK_PLL1_DIV2),
 	DEF_BASE("rcan", R8A7745_CLK_RCAN, CLK_TYPE_GEN2_RCAN,	CLK_USB_EXTAL),
 
-	DEF_FIXED("z2",    R8A7745_CLK_Z2,	CLK_PLL0,	    1, 1),
+	DEF_GEN3_Z("z2",   R8A77990_CLK_Z2,     CLK_TYPE_GEN3_Z2, CLK_PLL0, 4),
 	DEF_FIXED("zg",    R8A7745_CLK_ZG,	CLK_PLL1,	    6, 1),
 	DEF_FIXED("zx",    R8A7745_CLK_ZX,	CLK_PLL1,	    3, 1),
 	DEF_FIXED("zs",    R8A7745_CLK_ZS,	CLK_PLL1,	    6, 1),
-- 
2.11.0

RE: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock divider

[Biju Das]

Hi Simon,

Thanks for the patch

> Subject: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock
> divider
>
> On the RZ/G2E (r8a7745) SoC the Z2FC bits of the RFQCRC register, which
> control the frequency division ratio for the Z2φ clock are located at bit[12:8]
> rather than the more common location bit[4:0].
>
> This change is made with reference to the User's Manual v0.61.
>
> Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
>  drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-
> gen3-cpg.c
> index d21fdeb520e1..dfd2b9caeaf5 100644
> --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> @@ -450,6 +450,10 @@ static const struct soc_device_attribute
> cpg_quirks_match[] __initconst = {
>  .soc_id = "r8a77990",
>  .data = (void *)Z2FC_BIT_MASK_SFT_8,
>  },
> +{
> +.soc_id = "r8a7745",
> +.data = (void *)Z2FC_BIT_MASK_SFT_8,
> +},
>  { /* sentinel */ }
>  };


RZ/G2E  SoC id is r8a774c0.

Regards,
Biju



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

RE: [PATCH/RFT v2 6/6] clk: renesas: r8a7745: Implement Z2 as a variable clock

[Biju Das]

Hi Simon,

Thanks for the patch

> Subject: [PATCH/RFT v2 6/6] clk: renesas: r8a7745: Implement Z2 as a variable
> clock
>
> On the RZ/G2E (r8a7745) SoC the Z2 clock is not a fixed clock.
> Rather it is a clock with:

RZ/G2E SoC id is r8a774c0.


> * A parent of CLK_PLL0 running at 4.8GHz
> * A fixed divider of 4
> * A variable divider controlled by the Z2FC bits of the RFQCRC register
>
> This can be described using the DEF_GEN3_Z with a clock type of
> CLK_TYPE_GEN3_Z2.
>
> This change is made with reference to the User's Manual v0.61.
>
> Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
>  drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c
> b/drivers/clk/renesas/r8a7745-cpg-mssr.c
> index 493874e5ebee..f2ea72d9d663 100644
> --- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
> @@ -53,7 +53,7 @@ static const struct cpg_core_clk r8a7745_core_clks[]
> __initconst = {
>  DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,
> CLK_PLL1_DIV2),
>  DEF_BASE("rcan", R8A7745_CLK_RCAN, CLK_TYPE_GEN2_RCAN,
> CLK_USB_EXTAL),
>
> -DEF_FIXED("z2",    R8A7745_CLK_Z2,CLK_PLL0,    1, 1),
> +DEF_GEN3_Z("z2",   R8A77990_CLK_Z2,     CLK_TYPE_GEN3_Z2,
> CLK_PLL0, 4),

Looks like wrong file name.  it is supposed to be r8a774c0-cpg-mssr.c

>  DEF_FIXED("zg",    R8A7745_CLK_ZG,CLK_PLL1,    6, 1),
>  DEF_FIXED("zx",    R8A7745_CLK_ZX,CLK_PLL1,    3, 1),
>  DEF_FIXED("zs",    R8A7745_CLK_ZS,CLK_PLL1,    6, 1),
> --
> 2.11.0




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

Re: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock divider

[Simon Horman]

On Wed, Jan 30, 2019 at 09:43:31AM +0000, Biju Das wrote:
> Hi Simon,
> 
> Thanks for the patch
> 
> > Subject: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock
> > divider
> >
> > On the RZ/G2E (r8a7745) SoC the Z2FC bits of the RFQCRC register, which
> > control the frequency division ratio for the Z2φ clock are located at bit[12:8]
> > rather than the more common location bit[4:0].
> >
> > This change is made with reference to the User's Manual v0.61.
> >
> > Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> >  drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-
> > gen3-cpg.c
> > index d21fdeb520e1..dfd2b9caeaf5 100644
> > --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> > @@ -450,6 +450,10 @@ static const struct soc_device_attribute
> > cpg_quirks_match[] __initconst = {
> >  .soc_id = "r8a77990",
> >  .data = (void *)Z2FC_BIT_MASK_SFT_8,
> >  },
> > +{
> > +.soc_id = "r8a7745",
> > +.data = (void *)Z2FC_BIT_MASK_SFT_8,
> > +},
> >  { /* sentinel */ }
> >  };
> 
> 
> RZ/G2E  SoC id is r8a774c0.

Yikes! Silly me.

Re: [PATCH/RFT v2 6/6] clk: renesas: r8a7745: Implement Z2 as a variable clock

[Simon Horman]

On Wed, Jan 30, 2019 at 09:46:35AM +0000, Biju Das wrote:
> Hi Simon,
> 
> Thanks for the patch
> 
> > Subject: [PATCH/RFT v2 6/6] clk: renesas: r8a7745: Implement Z2 as a variable
> > clock
> >
> > On the RZ/G2E (r8a7745) SoC the Z2 clock is not a fixed clock.
> > Rather it is a clock with:
> 
> RZ/G2E SoC id is r8a774c0.

Sorry about that, somehow I got confused.

> > * A parent of CLK_PLL0 running at 4.8GHz
> > * A fixed divider of 4
> > * A variable divider controlled by the Z2FC bits of the RFQCRC register
> >
> > This can be described using the DEF_GEN3_Z with a clock type of
> > CLK_TYPE_GEN3_Z2.
> >
> > This change is made with reference to the User's Manual v0.61.
> >
> > Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> >  drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c
> > b/drivers/clk/renesas/r8a7745-cpg-mssr.c
> > index 493874e5ebee..f2ea72d9d663 100644
> > --- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
> > @@ -53,7 +53,7 @@ static const struct cpg_core_clk r8a7745_core_clks[]
> > __initconst = {
> >  DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,
> > CLK_PLL1_DIV2),
> >  DEF_BASE("rcan", R8A7745_CLK_RCAN, CLK_TYPE_GEN2_RCAN,
> > CLK_USB_EXTAL),
> >
> > -DEF_FIXED("z2",    R8A7745_CLK_Z2,CLK_PLL0,    1, 1),
> > +DEF_GEN3_Z("z2",   R8A77990_CLK_Z2,     CLK_TYPE_GEN3_Z2,
> > CLK_PLL0, 4),
> 
> Looks like wrong file name.  it is supposed to be r8a774c0-cpg-mssr.c
> 
> >  DEF_FIXED("zg",    R8A7745_CLK_ZG,CLK_PLL1,    6, 1),
> >  DEF_FIXED("zx",    R8A7745_CLK_ZX,CLK_PLL1,    3, 1),
> >  DEF_FIXED("zs",    R8A7745_CLK_ZS,CLK_PLL1,    6, 1),
> > --
> > 2.11.0
> 
> 
> 
> 
> Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
> 

RE: [PATCH/RFT v2 6/6] clk: renesas: r8a7745: Implement Z2 as a variable clock

[Fabrizio Castro]

Hello Simon,

Thank you for your patch!

> From: Simon Horman <horms+renesas@verge.net.au>
> Sent: 30 January 2019 09:40
> Subject: [PATCH/RFT v2 6/6] clk: renesas: r8a7745: Implement Z2 as a variable clock
>
> On the RZ/G2E (r8a7745) SoC the Z2 clock is not a fixed clock.

Did you mean RZ/G1E here?

> Rather it is a clock with:
>
> * A parent of CLK_PLL0 running at 4.8GHz
> * A fixed divider of 4
> * A variable divider controlled by the Z2FC bits of the RFQCRC register

My understanding is that those statements don't apply to the RZ/G1E, but they do apply to the RZ/G2E

>
> This can be described using the DEF_GEN3_Z with a clock type of
> CLK_TYPE_GEN3_Z2.
>
> This change is made with reference to the User's Manual v0.61.

That's the version of the User's Manual for the RZ/G2E, but this patch is for the RZ/G1E

>
> Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
>  drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
> index 493874e5ebee..f2ea72d9d663 100644
> --- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
> @@ -53,7 +53,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
>  DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,CLK_PLL1_DIV2),
>  DEF_BASE("rcan", R8A7745_CLK_RCAN, CLK_TYPE_GEN2_RCAN,CLK_USB_EXTAL),
>
> -DEF_FIXED("z2",    R8A7745_CLK_Z2,CLK_PLL0,    1, 1),
> +DEF_GEN3_Z("z2",   R8A77990_CLK_Z2,     CLK_TYPE_GEN3_Z2, CLK_PLL0, 4),

Perhaps this change was made to the wrong file?

Thanks,
Fab

>  DEF_FIXED("zg",    R8A7745_CLK_ZG,CLK_PLL1,    6, 1),
>  DEF_FIXED("zx",    R8A7745_CLK_ZX,CLK_PLL1,    3, 1),
>  DEF_FIXED("zs",    R8A7745_CLK_ZS,CLK_PLL1,    6, 1),
> --
> 2.11.0




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

RE: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock divider

[Fabrizio Castro]

Hello Simon,

> From: Biju Das
> Sent: 30 January 2019 09:44
> Subject: RE: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock divider
>
> Hi Simon,
>
> Thanks for the patch
>
> > Subject: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock
> > divider
> >
> > On the RZ/G2E (r8a7745) SoC the Z2FC bits of the RFQCRC register, which
> > control the frequency division ratio for the Z2φ clock are located at bit[12:8]
> > rather than the more common location bit[4:0].
> >
> > This change is made with reference to the User's Manual v0.61.
> >
> > Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> >  drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-
> > gen3-cpg.c
> > index d21fdeb520e1..dfd2b9caeaf5 100644
> > --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> > @@ -450,6 +450,10 @@ static const struct soc_device_attribute
> > cpg_quirks_match[] __initconst = {
> >  .soc_id = "r8a77990",
> >  .data = (void *)Z2FC_BIT_MASK_SFT_8,
> >  },
> > +{
> > +.soc_id = "r8a7745",
> > +.data = (void *)Z2FC_BIT_MASK_SFT_8,
> > +},
> >  { /* sentinel */ }
> >  };
>
>
> RZ/G2E  SoC id is r8a774c0.

+1

Cheers,
Fab

>
> Regards,
> Biju



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