RE: [PATCH/RFC] clk: renesas: r8a779a0: Add Z0 and Z1 clock support

[Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>]

Hi Geert-san,

Thank you for the patch!

> From: Geert Uytterhoeven, Sent: Friday, July 2, 2021 6:58 PM
> 
> Add support for the Z0 and Z1 (Cortex-A76 Sub-system 0 and 1) clocks,
> based on the existing support for Z clocks on R-Car Gen3.
> 
> As the offsets of the CPG_FRQCRB and CPG_FRQCRC registers on R-Car V3U
> differ from the offsets on other R-Car Gen3 SoCs, we cannot use the
> existing R-Car Gen3 support as-is.  For now, just make a copy, and
> change the register offsets.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Tested on Falcon by changing
> 
>     -#undef CLOCK_ALLOW_WRITE_DEBUGFS
>     +#define CLOCK_ALLOW_WRITE_DEBUGFS
> 
> in drivers/clk/clk.c, writing the desired clock rate to
> /sys/kernel/debug/clk/z0/clk_rate, and timing shell loops.
> The performance/clock rate looks fine over the full range from 56.25 MHz
> to 1.8 GHz.
> 
> RFC as it is not clear from the R-Car V3U User's Manual Rev. 0.5 if the
> CPG_FRQCRB.KICK bit applies to changes to CPG_FRQCRC or not:
>   - Section 8.2.12 ("Frequency Control Register B (FRQCRB)") says the
>     KICK bit activates the FRQCRB settings, but doesn't mention FRQCRC
>     like on R-Car Gen2 and Gen3,

The latest internal manual is also not clear about this unfortunately...

>   - Section 8.3 ("CPG Operation") says the KICK bit should be used when
>     changing Z0 or Z1.

I also understood it.

> Setting the KICK bit seems to work, and it is cleared automatically
> after 1 or 2 loops.

It looks good to me.

> The handling of Z clocks on R-Car Gen2, Gen3, and V3-U should be
> consolidated and moved to rcar-cpg-lib.c, so it can be shared by all
> clock drivers.

I think so. But, anyway,

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Best regards,
Yoshihiro Shimoda