From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Vinod <vkoul@kernel.org>,
"dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>
Subject: RE: [PATCH 1/2] dmaengine: rcar-dmac: Don't set DMACHCLR bit 0 to 1 if iommu is mapped
Date: Mon, 2 Sep 2019 09:21:50 +0000 [thread overview]
Message-ID: <TYAPR01MB4544C653A1E784F014650AFFD8BE0@TYAPR01MB4544.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <CAMuHMdUF4pgad0CWE6h4CQijy+-0Cif40C91TRVzH_OBO2tRPg@mail.gmail.com>
Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Monday, September 2, 2019 5:36 PM
>
> Hi Shimoda-san,
>
> On Wed, Aug 28, 2019 at 1:15 PM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > The commit 20c169aceb45 ("dmaengine: rcar-dmac: clear pertinence
> > number of channels") always set the DMACHCLR bit 0 to 1, but if
> > iommu is mapped to the device, this driver doesn't need to clear it.
> > So, this patch takes care of it by using "channels_mask" bitfield.
>
> Thanks for your patch!
>
> > Note that, this patch doesn't have a "Fixes:" tag because the driver
> > doesn't manage the channel 0 anyway so that the behavior of
> > the channel is not changed.
>
> This patch does fix a bug, as GENMASK(dmac->n_channels - 1, 0) doesn't
> take into account channels_offset. Hence it not only clears channel 0,
> as you mentioned, but also forgets to clear the last channel, which
> is a real bug.
Indeed.
> So I think this does warrant a
> Fixes: 20c169aceb459575 ("dmaengine: rcar-dmac: clear pertinence
> number of channels")
>
> Or perhaps the actual bug should be fixed first in a separate patch?
I think so. So, now I had already submitted two series like below, but
I'll fix this at first.
https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=165881
https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=166457
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thank you for your review!
> > --- a/drivers/dma/sh/rcar-dmac.c
> > +++ b/drivers/dma/sh/rcar-dmac.c
>
> > @@ -446,7 +448,7 @@ static int rcar_dmac_init(struct rcar_dmac *dmac)
> > u16 dmaor;
> >
> > /* Clear all channels and enable the DMAC globally. */
> > - rcar_dmac_write(dmac, RCAR_DMACHCLR, GENMASK(dmac->n_channels - 1, 0));
> > + rcar_dmac_write(dmac, RCAR_DMACHCLR, dmac->channels_mask);
> > rcar_dmac_write(dmac, RCAR_DMAOR,
> > RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME);
> >
> > @@ -822,6 +824,9 @@ static void rcar_dmac_stop_all_chan(struct rcar_dmac *dmac)
> > for (i = 0; i < dmac->n_channels; ++i) {
> > struct rcar_dmac_chan *chan = &dmac->channels[i];
> >
> > + if (!(dmac->channels_mask & BIT(i)))
> > + continue;
> > +
> > /* Stop and reinitialize the channel. */
> > spin_lock_irq(&chan->lock);
> > rcar_dmac_chan_halt(chan);
> > @@ -1801,6 +1806,8 @@ static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac)
> > return -EINVAL;
> > }
> >
> > + dmac->channels_mask = GENMASK(dmac->n_channels - 1, 0);
>
> You're aware dmac->n_channels can be 99, as per the check above, jut out of
> context? ;-)
>
> Probably that check should be changed to reject >= 32, as the hardware
> and driver don't support more than 32 bits in CHCLR anyway.
I got it. So, I'll fix the rcar_dmac_parse_of() as one more a separate patch.
Best regards,
Yoshihiro Shimoda
> > +
> > return 0;
> > }
> >
> > @@ -1810,7 +1817,6 @@ static int rcar_dmac_probe(struct platform_device *pdev)
> > DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES |
> > DMA_SLAVE_BUSWIDTH_8_BYTES | DMA_SLAVE_BUSWIDTH_16_BYTES |
> > DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES;
> > - unsigned int channels_offset = 0;
> > struct dma_device *engine;
> > struct rcar_dmac *dmac;
> > const struct rcar_dmac_of_data *data;
> > @@ -1843,10 +1849,8 @@ static int rcar_dmac_probe(struct platform_device *pdev)
> > * level we can't disable it selectively, so ignore channel 0 for now if
> > * the device is part of an IOMMU group.
> > */
> > - if (device_iommu_mapped(&pdev->dev)) {
> > - dmac->n_channels--;
> > - channels_offset = 1;
> > - }
> > + if (device_iommu_mapped(&pdev->dev))
> > + dmac->channels_mask &= ~BIT(0);
> >
> > dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels,
> > sizeof(*dmac->channels), GFP_KERNEL);
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
next prev parent reply other threads:[~2019-09-02 9:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-28 11:13 [PATCH 0/2] dmaengine: rcar-dmac: Add dma-channel-mask property support Yoshihiro Shimoda
2019-08-28 11:13 ` [PATCH 1/2] dmaengine: rcar-dmac: Don't set DMACHCLR bit 0 to 1 if iommu is mapped Yoshihiro Shimoda
2019-08-31 8:49 ` Simon Horman
2019-09-02 8:36 ` Geert Uytterhoeven
2019-09-02 9:21 ` Yoshihiro Shimoda [this message]
2019-09-02 8:52 ` Geert Uytterhoeven
2019-09-02 9:25 ` Yoshihiro Shimoda
2019-08-28 11:13 ` [PATCH 2/2] dmaengine: rcar-dmac: Add dma-channel-mask property support Yoshihiro Shimoda
2019-08-31 8:50 ` Simon Horman
2019-09-02 8:50 ` Geert Uytterhoeven
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