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charset="Windows-1252" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TYCPR01MB10588.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4c18eb28-d5ea-4579-4655-08da90a98cd7 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Sep 2022 08:18:31.2669 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jem70ZjPz2E0Q/UahqvBdjp7r1QHdi450DTr1axuEz8XM/8mUQGeIWNzE0Ttu6ukLxWS5xgecEC4HaDBuwErXnQsN/CGhfh1tZzRBIuS3D0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYBPR01MB5407 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hello Conor, Thank you for your interest. > From: Conor.Dooley@microchip.com > Sent: 06 September 2022 11:39 >=20 > On 06/09/2022 11:21, Lad Prabhakar wrote: >=20 > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.= h > > index 2a0ef738695e..10a7c855d125 100644 > > --- a/arch/riscv/include/asm/sbi.h > > +++ b/arch/riscv/include/asm/sbi.h > > @@ -37,6 +37,7 @@ enum sbi_ext_id { > > > > /* Vendor extensions must lie within this range */ > > SBI_EXT_VENDOR_START =3D 0x09000000, > > + SBI_EXT_ANDES =3D 0x0900031E, > > SBI_EXT_VENDOR_END =3D 0x09FFFFFF, > > }; >=20 > Everything else aside, I am very interested in what's happening > here. I'll take a proper look through things later, but for now: >=20 > For PolarFire SoC we have an InterHart Communication SBI EXT that > would would like to upstream support for. We are not aiming to put > the driver itself in arch/riscv - it's just a mailbox driver, but > I would like to use sbi.h for defining the vendor id etc. >=20 > I am not sure how this all aligns with: > > We=92ll only accept patches for new modules or extensions if the > > specifications for those modules or extensions are listed as being > > =93Frozen=94 or =93Ratified=94 by the RISC-V Foundation. (Developers ma= y, of > > course, maintain their own Linux kernel trees that contain code for > > any draft extensions that they wish.) > > > > Additionally, the RISC-V specification allows implementors to create > > their own custom extensions. These custom extensions aren=92t required > > to go through any review or ratification process by the RISC-V > > Foundation. To avoid the maintenance complexity and potential > > performance impact of adding kernel code for implementor-specific > > RISC-V extensions, we=92ll only to accept patches for extensions that > > have been officially frozen or ratified by the RISC-V Foundation. > > (Implementors, may, of course, maintain their own Linux kernel trees > > containing code for any custom extensions that they wish.) >=20 > Which is in: https://docs.kernel.org/riscv/patch-acceptance.html >=20 > It is unclear to me whether that is just for ISA extensions or if that > covers SBI extensions too. At least for us, since we don't touch arch > code there is relatively little friction & there's no concerns about > reducing the portability of a kernel since it is just a regular old > driver. >=20 > I was planning on cornering some people *cough* Palmer *cough* at > LPC and asking him what his thoughts were there. >=20 > FWIW this is what we have been doing: > https://github.com/linux4microchip/linux/blob/linux-5.15-mchp/drivers/mai= lbox/mailbox-miv-ihc.c#L27 >=20 > The IP itself has not stabilised yet, so we have not sent any patches > yet, but we do intend doing so... >=20 > But yea, I'll take a properly look at what you're doing here soonTM, > although at this point it may be the other side of LPC. >=20 > btw, where can I get my hands on your hardware? The latest information I have is that it should be available via various di= stributors on the 21st Sept. Kind regards, Chris >=20 > Thanks, > Conor. >=20