On Mon, Sep 26, 2022 at 06:10:02PM +0100, Biju Das wrote:
> Due to clk rounding errors on RZ/G2L platforms, it selects a clock source
> with a lower clock rate compared to a higher one.
> For eg: The rounding error (533333333 Hz / 4 * 4 = 533333332 Hz < 5333333
> 33 Hz) selects a clk source of 400 MHz instead of 533.333333 MHz.
> 
> This patch fixes this issue by adding a margin of (1/1024) higher to
> the clock rate.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Looks very good to me now! Thanks for keeping at it:

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>