From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: linux-renesas-soc@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-clk@vger.kernel.org
Subject: [PATCH] clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks
Date: Fri, 27 Sep 2019 21:09:21 +0300 [thread overview]
Message-ID: <be27a344-d8bf-9e0c-8950-2d1b48498496@cogentembedded.com> (raw)
In-Reply-To: <f1c53dd5-2dc5-9f11-44e3-8e222ed21903@cogentembedded.com>
I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
clk_register_composite() when registering the RPC[D2] clocks...
Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'clk-renesas' branch of Geert Uytterhoeven's
'renesas-drivers.git' repo.
drivers/clk/renesas/rcar-gen3-cpg.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
Index: renesas/drivers/clk/renesas/rcar-gen3-cpg.c
===================================================================
--- renesas.orig/drivers/clk/renesas/rcar-gen3-cpg.c
+++ renesas/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -464,7 +464,8 @@ static struct clk * __init cpg_rpc_clk_r
clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
&rpc->div.hw, &clk_divider_ops,
- &rpc->gate.hw, &clk_gate_ops, 0);
+ &rpc->gate.hw, &clk_gate_ops,
+ CLK_SET_RATE_PARENT);
if (IS_ERR(clk)) {
kfree(rpc);
return clk;
@@ -500,7 +501,8 @@ static struct clk * __init cpg_rpcd2_clk
clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
&rpcd2->fixed.hw, &clk_fixed_factor_ops,
- &rpcd2->gate.hw, &clk_gate_ops, 0);
+ &rpcd2->gate.hw, &clk_gate_ops,
+ CLK_SET_RATE_PARENT);
if (IS_ERR(clk))
kfree(rpcd2);
next prev parent reply other threads:[~2019-09-27 18:09 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-22 19:55 [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Sergei Shtylyov
2019-01-22 19:57 ` [PATCH v3 1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify() Sergei Shtylyov
2019-01-22 19:58 ` [PATCH v3 2/4] clk: renesas: rcar-gen3-cpg: add spinlock Sergei Shtylyov
2019-01-22 19:59 ` [PATCH v3 3/4] clk: renesas: rcar-gen3-cpg: add RPC clocks Sergei Shtylyov
2019-01-25 10:25 ` Geert Uytterhoeven
2019-01-22 20:01 ` [PATCH v3 4/4] clk: renesas: r8a77980-cpg-mssr: " Sergei Shtylyov
2019-01-25 10:25 ` [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Geert Uytterhoeven
2019-03-07 19:53 ` [PATCH] clk: renesas: r8a77980-cpg-mssr: fix RPC-IF module clock's parent Sergei Shtylyov
2019-03-11 9:30 ` Geert Uytterhoeven
2019-03-11 17:14 ` Sergei Shtylyov
2019-03-11 19:10 ` Sergei Shtylyov
2019-09-27 18:09 ` Sergei Shtylyov [this message]
2019-10-07 11:45 ` [PATCH] clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks Geert Uytterhoeven
2019-10-07 11:49 ` Sergei Shtylyov
2019-12-17 20:43 ` Geert Uytterhoeven
2019-12-18 19:34 ` Sergei Shtylyov
2019-12-20 14:31 ` Geert Uytterhoeven
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