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* [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support
@ 2019-01-22 19:55 Sergei Shtylyov
  2019-01-22 19:57 ` [PATCH v3 1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify() Sergei Shtylyov
                   ` (6 more replies)
  0 siblings, 7 replies; 17+ messages in thread
From: Sergei Shtylyov @ 2019-01-22 19:55 UTC (permalink / raw)
  To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

Hello!

Here's the set of 4 patches against the 'clk-renesas' branch of Geert Uytterhoeven's
'renesas-drivers.git' repo. We're adding support for the R8A77980 CPG/MSSR RPC clocks...

[1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify()
[2/4] clk: renesas: rcar-gen3-cpg: add spinlock
[3/4] clk: renesas: rcar-gen3-cpg: add RPC clocks
[4/4] clk: renesas: r8a77980-cpg-mssr: add RPC clocks

MBR, Sergei

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v3 1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify()
  2019-01-22 19:55 [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Sergei Shtylyov
@ 2019-01-22 19:57 ` Sergei Shtylyov
  2019-01-22 19:58 ` [PATCH v3 2/4] clk: renesas: rcar-gen3-cpg: add spinlock Sergei Shtylyov
                   ` (5 subsequent siblings)
  6 siblings, 0 replies; 17+ messages in thread
From: Sergei Shtylyov @ 2019-01-22 19:57 UTC (permalink / raw)
  To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

There's quite often repeated sequence of a CPG register read-modify-write,
so it seems worth factoring it out into a function -- this saves 68 bytes
of the object code (AArch64 gcc 4.8.5) and simplifies protecting all such
sequences with a spinlock in the next patch...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

---
Changes in version 3:
- refreshed the patch;
- added Geert's tag.

Changes in version 2:
- moved the readl() call from the initializer in cpg_reg_modify();
- adjusted the patch description.

 drivers/clk/renesas/rcar-gen3-cpg.c |   38 ++++++++++++++++++------------------
 1 file changed, 20 insertions(+), 18 deletions(-)

Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.c
+++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -30,6 +30,16 @@
 
 #define CPG_RCKCR_CKSEL	BIT(15)	/* RCLK Clock Source Select */
 
+static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
+{
+	u32 val;
+
+	val = readl(reg);
+	val &= ~clear;
+	val |= set;
+	writel(val, reg);
+};
+
 struct cpg_simple_notifier {
 	struct notifier_block nb;
 	void __iomem *reg;
@@ -118,7 +128,6 @@ static int cpg_z_clk_set_rate(struct clk
 	struct cpg_z_clk *zclk = to_z_clk(hw);
 	unsigned int mult;
 	unsigned int i;
-	u32 val, kick;
 
 	/* Factor of 2 is for fixed divider */
 	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);
@@ -127,17 +136,14 @@ static int cpg_z_clk_set_rate(struct clk
 	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
 		return -EBUSY;
 
-	val = readl(zclk->reg) & ~zclk->mask;
-	val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask;
-	writel(val, zclk->reg);
+	cpg_reg_modify(zclk->reg, zclk->mask,
+		       ((32 - mult) << __ffs(zclk->mask)) & zclk->mask);
 
 	/*
 	 * Set KICK bit in FRQCRB to update hardware setting and wait for
 	 * clock change completion.
 	 */
-	kick = readl(zclk->kick_reg);
-	kick |= CPG_FRQCRB_KICK;
-	writel(kick, zclk->kick_reg);
+	cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
 
 	/*
 	 * Note: There is no HW information about the worst case latency.
@@ -266,12 +272,10 @@ static const struct sd_div_table cpg_sd_
 static int cpg_sd_clock_enable(struct clk_hw *hw)
 {
 	struct sd_clock *clock = to_sd_clock(hw);
-	u32 val = readl(clock->csn.reg);
-
-	val &= ~(CPG_SD_STP_MASK);
-	val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK;
 
-	writel(val, clock->csn.reg);
+	cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK,
+		       clock->div_table[clock->cur_div_idx].val &
+		       CPG_SD_STP_MASK);
 
 	return 0;
 }
@@ -280,7 +284,7 @@ static void cpg_sd_clock_disable(struct
 {
 	struct sd_clock *clock = to_sd_clock(hw);
 
-	writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg);
+	cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK);
 }
 
 static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
@@ -327,7 +331,6 @@ static int cpg_sd_clock_set_rate(struct
 {
 	struct sd_clock *clock = to_sd_clock(hw);
 	unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
-	u32 val;
 	unsigned int i;
 
 	for (i = 0; i < clock->div_num; i++)
@@ -339,10 +342,9 @@ static int cpg_sd_clock_set_rate(struct
 
 	clock->cur_div_idx = i;
 
-	val = readl(clock->csn.reg);
-	val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
-	val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
-	writel(val, clock->csn.reg);
+	cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK,
+		       clock->div_table[i].val &
+		       (CPG_SD_STP_MASK | CPG_SD_FC_MASK));
 
 	return 0;
 }

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v3 2/4] clk: renesas: rcar-gen3-cpg: add spinlock
  2019-01-22 19:55 [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Sergei Shtylyov
  2019-01-22 19:57 ` [PATCH v3 1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify() Sergei Shtylyov
@ 2019-01-22 19:58 ` Sergei Shtylyov
  2019-01-22 19:59 ` [PATCH v3 3/4] clk: renesas: rcar-gen3-cpg: add RPC clocks Sergei Shtylyov
                   ` (4 subsequent siblings)
  6 siblings, 0 replies; 17+ messages in thread
From: Sergei Shtylyov @ 2019-01-22 19:58 UTC (permalink / raw)
  To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

Protect the CPG register read-modify-write sequence with a spinlock.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

---
Changes in version 3:
- refreshed the patch;
- added Geert's tag.

Changes in version 2:
- new patch.

 drivers/clk/renesas/rcar-gen3-cpg.c |    8 ++++++++
 1 file changed, 8 insertions(+)

Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.c
+++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -30,14 +30,19 @@
 
 #define CPG_RCKCR_CKSEL	BIT(15)	/* RCLK Clock Source Select */
 
+static spinlock_t cpg_lock;
+
 static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
 {
+	unsigned long flags;
 	u32 val;
 
+	spin_lock_irqsave(&cpg_lock, flags);
 	val = readl(reg);
 	val &= ~clear;
 	val |= set;
 	writel(val, reg);
+	spin_unlock_irqrestore(&cpg_lock, flags);
 };
 
 struct cpg_simple_notifier {
@@ -615,5 +620,8 @@ int __init rcar_gen3_cpg_init(const stru
 	if (attr)
 		cpg_quirks = (uintptr_t)attr->data;
 	pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
+
+	spin_lock_init(&cpg_lock);
+
 	return 0;
 }


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v3 3/4] clk: renesas: rcar-gen3-cpg: add RPC clocks
  2019-01-22 19:55 [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Sergei Shtylyov
  2019-01-22 19:57 ` [PATCH v3 1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify() Sergei Shtylyov
  2019-01-22 19:58 ` [PATCH v3 2/4] clk: renesas: rcar-gen3-cpg: add spinlock Sergei Shtylyov
@ 2019-01-22 19:59 ` Sergei Shtylyov
  2019-01-25 10:25   ` Geert Uytterhoeven
  2019-01-22 20:01 ` [PATCH v3 4/4] clk: renesas: r8a77980-cpg-mssr: " Sergei Shtylyov
                   ` (3 subsequent siblings)
  6 siblings, 1 reply; 17+ messages in thread
From: Sergei Shtylyov @ 2019-01-22 19:59 UTC (permalink / raw)
  To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all
the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field
is different between SoCs; it makes sense to support the most common case
of this encoding in the R-Car gen3 CPG driver...

After adding the RPCSRC clock, we can add the RPC[D2] clocks derived from
it and controlled by the RPCCKCR register on all the R-Car gen3 SoCs except
V3M (R8A77970); the composite clock driver seems handy for this task, using
the spinlock added in the previous patch...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
Changes in version 3:
- added 'struct rpcd2_clock' embracing both 'struct clk_fixed_factor' and
  'struct clk_gate' to reduce the # of kzalloc() calls;
- added a comment about the single notifier to 'struct rpc_clock';
- refreshed the patch.

Changes in version 2:
- merged in the RPCD2 clock support from the next patch;
- moved in the RPCSRC clock support from the R8A77980 CPG/MSSR driver patch;
- switched the RPC and RPCSD2 clock support to the composite clock driver;
- changed the 1st parameter of cpg_rpc[d2]_clk_register();
- rewrote the patch description, renamed the patch.

 drivers/clk/renesas/rcar-gen3-cpg.c |   99 ++++++++++++++++++++++++++++++++++++
 drivers/clk/renesas/rcar-gen3-cpg.h |    4 +
 2 files changed, 103 insertions(+)

Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.c
+++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -422,6 +422,90 @@ free_clock:
 	return clk;
 }
 
+struct rpc_clock {
+	struct clk_divider div;
+	struct clk_gate gate;
+	/*
+	 * One notifier covers both RPC and RPCD2 clocks as they are both
+	 * controlled by the same RPCCKCR register...
+	 */
+	struct cpg_simple_notifier csn;
+};
+
+static const struct clk_div_table cpg_rpcsrc_div_table[] = {
+	{ 2, 5 }, { 3, 6 }, { 0, 0 },
+};
+
+static const struct clk_div_table cpg_rpc_div_table[] = {
+	{ 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
+};
+
+static struct clk * __init cpg_rpc_clk_register(const char *name,
+	void __iomem *base, const char *parent_name,
+	struct raw_notifier_head *notifiers)
+{
+	struct rpc_clock *rpc;
+	struct clk *clk;
+
+	rpc = kzalloc(sizeof(*rpc), GFP_KERNEL);
+	if (!rpc)
+		return ERR_PTR(-ENOMEM);
+
+	rpc->div.reg = base + CPG_RPCCKCR;
+	rpc->div.width = 3;
+	rpc->div.table = cpg_rpc_div_table;
+	rpc->div.lock = &cpg_lock;
+
+	rpc->gate.reg = base + CPG_RPCCKCR;
+	rpc->gate.bit_idx = 8;
+	rpc->gate.flags = CLK_GATE_SET_TO_DISABLE;
+	rpc->gate.lock = &cpg_lock;
+
+	rpc->csn.reg = base + CPG_RPCCKCR;
+
+	clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
+				     &rpc->div.hw,  &clk_divider_ops,
+				     &rpc->gate.hw, &clk_gate_ops, 0);
+	if (IS_ERR(clk))
+		kfree(rpc);
+
+	cpg_simple_notifier_register(notifiers, &rpc->csn);
+	return clk;
+}
+
+struct rpc2_clock {
+	struct clk_fixed_factor fixed;
+	struct clk_gate gate;
+};
+
+static struct clk * __init cpg_rpcd2_clk_register(const char *name,
+						  void __iomem *base,
+						  const char *parent_name)
+{
+	struct rpc2_clock *rpc2;
+	struct clk *clk;
+
+	rpc2 = kzalloc(sizeof(*rpc2), GFP_KERNEL);
+	if (!rpc2)
+		return ERR_PTR(-ENOMEM);
+
+	rpc2->fixed.mult = 1;
+	rpc2->fixed.div = 2;
+
+	rpc2->gate.reg = base + CPG_RPCCKCR;
+	rpc2->gate.bit_idx = 9;
+	rpc2->gate.flags = CLK_GATE_SET_TO_DISABLE;
+	rpc2->gate.lock = &cpg_lock;
+
+	clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
+				     &rpc2->fixed.hw, &clk_fixed_factor_ops,
+				     &rpc2->gate.hw, &clk_gate_ops, 0);
+	if (IS_ERR(clk))
+		kfree(rpc2);
+
+	return clk;
+}
+
 
 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
 static unsigned int cpg_clk_extalr __initdata;
@@ -600,6 +684,21 @@ struct clk * __init rcar_gen3_cpg_clk_re
 		}
 		break;
 
+	case CLK_TYPE_GEN3_RPCSRC:
+		return clk_register_divider_table(NULL, core->name,
+						  __clk_get_name(parent), 0,
+						  base + CPG_RPCCKCR, 3, 2, 0,
+						  cpg_rpcsrc_div_table,
+						  &cpg_lock);
+
+	case CLK_TYPE_GEN3_RPC:
+		return cpg_rpc_clk_register(core->name, base,
+					    __clk_get_name(parent), notifiers);
+
+	case CLK_TYPE_GEN3_RPCD2:
+		return cpg_rpcd2_clk_register(core->name, base,
+					      __clk_get_name(parent));
+
 	default:
 		return ERR_PTR(-EINVAL);
 	}
Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.h
+++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -23,6 +23,9 @@ enum rcar_gen3_clk_types {
 	CLK_TYPE_GEN3_Z2,
 	CLK_TYPE_GEN3_OSC,	/* OSC EXTAL predivider and fixed divider */
 	CLK_TYPE_GEN3_RCKSEL,	/* Select parent/divider using RCKCR.CKSEL */
+	CLK_TYPE_GEN3_RPCSRC,
+	CLK_TYPE_GEN3_RPC,
+	CLK_TYPE_GEN3_RPCD2,
 
 	/* SoC specific definitions start here */
 	CLK_TYPE_GEN3_SOC_BASE,
@@ -57,6 +60,7 @@ struct rcar_gen3_cpg_pll_config {
 	u8 osc_prediv;
 };
 
+#define CPG_RPCCKCR	0x238
 #define CPG_RCKCR	0x240
 
 struct clk *rcar_gen3_cpg_clk_register(struct device *dev,


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v3 4/4] clk: renesas: r8a77980-cpg-mssr: add RPC clocks
  2019-01-22 19:55 [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Sergei Shtylyov
                   ` (2 preceding siblings ...)
  2019-01-22 19:59 ` [PATCH v3 3/4] clk: renesas: rcar-gen3-cpg: add RPC clocks Sergei Shtylyov
@ 2019-01-22 20:01 ` Sergei Shtylyov
  2019-01-25 10:25 ` [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Geert Uytterhoeven
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 17+ messages in thread
From: Sergei Shtylyov @ 2019-01-22 20:01 UTC (permalink / raw)
  To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the R-Car V3H (R8A77980) CPG/MSSR
driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

---
Changes in version 3:
- added Geert's tag.

Changes in version 2:
- moved the RPCSRC clock support to the R-Car gen3 CPG patch adding the RPC
  clocks;
- rewrote the patch description.

 drivers/clk/renesas/r8a77980-cpg-mssr.c |    8 ++++++++
 1 file changed, 8 insertions(+)

Index: renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -41,6 +41,7 @@ enum clk_ids {
 	CLK_S2,
 	CLK_S3,
 	CLK_SDSRC,
+	CLK_RPCSRC,
 	CLK_OCO,
 
 	/* Module Clocks */
@@ -65,8 +66,14 @@ static const struct cpg_core_clk r8a7798
 	DEF_FIXED(".s2",	CLK_S2,		   CLK_PLL1_DIV2,  4, 1),
 	DEF_FIXED(".s3",	CLK_S3,		   CLK_PLL1_DIV2,  6, 1),
 	DEF_FIXED(".sdsrc",	CLK_SDSRC,	   CLK_PLL1_DIV2,  2, 1),
+	DEF_BASE(".rpcsrc",	CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
 	DEF_RATE(".oco",	CLK_OCO,           32768),
 
+	DEF_BASE("rpc",		R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
+		 CLK_RPCSRC),
+	DEF_BASE("rpcd2",	R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+		 R8A77980_CLK_RPC),
+
 	/* Core Clock Outputs */
 	DEF_FIXED("ztr",	R8A77980_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
 	DEF_FIXED("ztrd2",	R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
@@ -164,6 +171,7 @@ static const struct mssr_mod_clk r8a7798
 	DEF_MOD("gpio1",		 911,	R8A77980_CLK_CP),
 	DEF_MOD("gpio0",		 912,	R8A77980_CLK_CP),
 	DEF_MOD("can-fd",		 914,	R8A77980_CLK_S3D2),
+	DEF_MOD("rpc-if",		 917,	R8A77980_CLK_RPC),
 	DEF_MOD("i2c4",			 927,	R8A77980_CLK_S0D6),
 	DEF_MOD("i2c3",			 928,	R8A77980_CLK_S0D6),
 	DEF_MOD("i2c2",			 929,	R8A77980_CLK_S3D2),

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v3 3/4] clk: renesas: rcar-gen3-cpg: add RPC clocks
  2019-01-22 19:59 ` [PATCH v3 3/4] clk: renesas: rcar-gen3-cpg: add RPC clocks Sergei Shtylyov
@ 2019-01-25 10:25   ` Geert Uytterhoeven
  0 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2019-01-25 10:25 UTC (permalink / raw)
  To: Sergei Shtylyov
  Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

On Tue, Jan 22, 2019 at 8:59 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all
> the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field
> is different between SoCs; it makes sense to support the most common case
> of this encoding in the R-Car gen3 CPG driver...
>
> After adding the RPCSRC clock, we can add the RPC[D2] clocks derived from
> it and controlled by the RPCCKCR register on all the R-Car gen3 SoCs except
> V3M (R8A77970); the composite clock driver seems handy for this task, using
> the spinlock added in the previous patch...
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> Changes in version 3:
> - added 'struct rpcd2_clock' embracing both 'struct clk_fixed_factor' and
>   'struct clk_gate' to reduce the # of kzalloc() calls;
> - added a comment about the single notifier to 'struct rpc_clock';
> - refreshed the patch.

Thanks for the update!

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> --- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.c
> +++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c

> +struct rpc2_clock {

rpcd2

> +       struct clk_fixed_factor fixed;
> +       struct clk_gate gate;
> +};
> +
> +static struct clk * __init cpg_rpcd2_clk_register(const char *name,
> +                                                 void __iomem *base,
> +                                                 const char *parent_name)
> +{
> +       struct rpc2_clock *rpc2;

rpcd2 (twice)

No need to resend, fixing up while applying.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support
  2019-01-22 19:55 [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Sergei Shtylyov
                   ` (3 preceding siblings ...)
  2019-01-22 20:01 ` [PATCH v3 4/4] clk: renesas: r8a77980-cpg-mssr: " Sergei Shtylyov
@ 2019-01-25 10:25 ` Geert Uytterhoeven
  2019-03-07 19:53 ` [PATCH] clk: renesas: r8a77980-cpg-mssr: fix RPC-IF module clock's parent Sergei Shtylyov
  2019-09-27 18:09 ` [PATCH] clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks Sergei Shtylyov
  6 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2019-01-25 10:25 UTC (permalink / raw)
  To: Sergei Shtylyov
  Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

Hi Sergei,

On Tue, Jan 22, 2019 at 8:55 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Here's the set of 4 patches against the 'clk-renesas' branch of Geert Uytterhoeven's
> 'renesas-drivers.git' repo. We're adding support for the R8A77980 CPG/MSSR RPC clocks...
>
> [1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify()
> [2/4] clk: renesas: rcar-gen3-cpg: add spinlock
> [3/4] clk: renesas: rcar-gen3-cpg: add RPC clocks
> [4/4] clk: renesas: r8a77980-cpg-mssr: add RPC clocks

Thank you, queuing in clk-renesas-for-v5.1...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH] clk: renesas: r8a77980-cpg-mssr: fix RPC-IF module clock's parent
  2019-01-22 19:55 [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Sergei Shtylyov
                   ` (4 preceding siblings ...)
  2019-01-25 10:25 ` [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Geert Uytterhoeven
@ 2019-03-07 19:53 ` Sergei Shtylyov
  2019-03-11  9:30   ` Geert Uytterhoeven
  2019-09-27 18:09 ` [PATCH] clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks Sergei Shtylyov
  6 siblings, 1 reply; 17+ messages in thread
From: Sergei Shtylyov @ 2019-03-07 19:53 UTC (permalink / raw)
  To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

Testing has shown that the RPC-IF module clock's parent is the RPCD2 clock,
not the RPC one -- the RPC-IF register reads stall otherwise...

Fixes: 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
This patch is against the 'clk-renesas' branch of Geert Uytterhoeven's
'renesas-drivers.git' repo.

 drivers/clk/renesas/r8a77980-cpg-mssr.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Index: renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -171,7 +171,7 @@ static const struct mssr_mod_clk r8a7798
 	DEF_MOD("gpio1",		 911,	R8A77980_CLK_CP),
 	DEF_MOD("gpio0",		 912,	R8A77980_CLK_CP),
 	DEF_MOD("can-fd",		 914,	R8A77980_CLK_S3D2),
-	DEF_MOD("rpc-if",		 917,	R8A77980_CLK_RPC),
+	DEF_MOD("rpc-if",		 917,	R8A77980_CLK_RPCD2),
 	DEF_MOD("i2c4",			 927,	R8A77980_CLK_S0D6),
 	DEF_MOD("i2c3",			 928,	R8A77980_CLK_S0D6),
 	DEF_MOD("i2c2",			 929,	R8A77980_CLK_S3D2),

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH] clk: renesas: r8a77980-cpg-mssr: fix RPC-IF module clock's parent
  2019-03-07 19:53 ` [PATCH] clk: renesas: r8a77980-cpg-mssr: fix RPC-IF module clock's parent Sergei Shtylyov
@ 2019-03-11  9:30   ` Geert Uytterhoeven
  2019-03-11 17:14     ` Sergei Shtylyov
  0 siblings, 1 reply; 17+ messages in thread
From: Geert Uytterhoeven @ 2019-03-11  9:30 UTC (permalink / raw)
  To: Sergei Shtylyov
  Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

Hi Sergei,

Thanks for your patch!

On Thu, Mar 7, 2019 at 8:53 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Testing has shown that the RPC-IF module clock's parent is the RPCD2 clock,
> not the RPC one -- the RPC-IF register reads stall otherwise...

Perhaps... Or something else is wrong with how the RPC driver uses the
clock hierarchy.
According to the docs, RPC clocks RPC-PHY, and RPCD2 clocks RPC-LINK.
Currently nothing references RPCD2, so it is disabled automatically.
If you make RPC -> RPCD2 -> RPC-IF, enabling RPC-IF indeed enables
both RPC and RPCD2.

Perhaps the RPC device node does need a reference to RPCD2?

Is this also the case on R-Car V3M, where RPCD2 is not controlled by the
CPG, but by the DIVREG register in the RPC-IF module itself?

See also section 62.4.7 (Frequency change), which does not have a
subsection for V3H, but it may be impacted (changing RPCD2 causes
an additional read of RPCCKR, satisfying the read-after-write requirement
documented there).

> Fixes: 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks")
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

> --- renesas-drivers.orig/drivers/clk/renesas/r8a77980-cpg-mssr.c
> +++ renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
> @@ -171,7 +171,7 @@ static const struct mssr_mod_clk r8a7798
>         DEF_MOD("gpio1",                 911,   R8A77980_CLK_CP),
>         DEF_MOD("gpio0",                 912,   R8A77980_CLK_CP),
>         DEF_MOD("can-fd",                914,   R8A77980_CLK_S3D2),
> -       DEF_MOD("rpc-if",                917,   R8A77980_CLK_RPC),
> +       DEF_MOD("rpc-if",                917,   R8A77980_CLK_RPCD2),
>         DEF_MOD("i2c4",                  927,   R8A77980_CLK_S0D6),
>         DEF_MOD("i2c3",                  928,   R8A77980_CLK_S0D6),
>         DEF_MOD("i2c2",                  929,   R8A77980_CLK_S3D2),

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH] clk: renesas: r8a77980-cpg-mssr: fix RPC-IF module clock's parent
  2019-03-11  9:30   ` Geert Uytterhoeven
@ 2019-03-11 17:14     ` Sergei Shtylyov
  2019-03-11 19:10       ` Sergei Shtylyov
  0 siblings, 1 reply; 17+ messages in thread
From: Sergei Shtylyov @ 2019-03-11 17:14 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

On 03/11/2019 12:30 PM, Geert Uytterhoeven wrote:

>> Testing has shown that the RPC-IF module clock's parent is the RPCD2 clock,
>> not the RPC one -- the RPC-IF register reads stall otherwise...
> 
> Perhaps... Or something else is wrong with how the RPC driver uses the
> clock hierarchy.

   Yes, explicitly enabling RPCD2 did help as well.

> According to the docs, RPC clocks RPC-PHY, and RPCD2 clocks RPC-LINK.

   I've also read the manual. Note it's not that reading a PHY register
hangs the kernel but reading CMNCR...

> Currently nothing references RPCD2, so it is disabled automatically.

  Only on V3H.

> If you make RPC -> RPCD2 -> RPC-IF, enabling RPC-IF indeed enables
> both RPC and RPCD2.

   Sure, it does. :-)

> Perhaps the RPC device node does need a reference to RPCD2?

   Looks like that wouldn't hurt either...

> Is this also the case on R-Car V3M, where RPCD2 is not controlled by the
> CPG, but by the DIVREG register in the RPC-IF module itself?

   No hangs were seen on V3M, despite the RPCD2 clock remained disabled.
The RPC clocks on both V3H and V3M suffer from a lack of clear documentation...

> See also section 62.4.7 (Frequency change), which does not have a
> subsection for V3H, but it may be impacted (changing RPCD2 causes
> an additional read of RPCCKR, satisfying the read-after-write requirement
> documented there).

   Hmm, haven't seen this item before; it looks like we can't use the standard
divider component. BTW, this section in the 1.50 manual tells to use the soft
reset on V3MOK. OK, I'll investigate this...

>> Fixes: 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks")
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
[...]

MBR, Sergei

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH] clk: renesas: r8a77980-cpg-mssr: fix RPC-IF module clock's parent
  2019-03-11 17:14     ` Sergei Shtylyov
@ 2019-03-11 19:10       ` Sergei Shtylyov
  0 siblings, 0 replies; 17+ messages in thread
From: Sergei Shtylyov @ 2019-03-11 19:10 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

On 03/11/2019 08:14 PM, Sergei Shtylyov wrote:

[...]

>    No hangs were seen on V3M, despite the RPCD2 clock remained disabled.
> The RPC clocks on both V3H and V3M suffer from a lack of clear documentation...
> 
>> See also section 62.4.7 (Frequency change), which does not have a
>> subsection for V3H, but it may be impacted (changing RPCD2 causes
>> an additional read of RPCCKR, satisfying the read-after-write requirement
>> documented there).
> 
>    Hmm, haven't seen this item before; it looks like we can't use the standard
> divider component. BTW, this section in the 1.50 manual tells to use the soft
> reset on V3MOK. OK, I'll investigate this...

   Now I have: the frequency change didn't seem to  happen, and without RPCD2 enabled
the CMNCR read still hangs, even when I added readl() call into clk_writel(). So I
think my patch was correct.

>>> Fixes:  94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks")
>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> [...]

MBR, Sergei

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH] clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks
  2019-01-22 19:55 [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Sergei Shtylyov
                   ` (5 preceding siblings ...)
  2019-03-07 19:53 ` [PATCH] clk: renesas: r8a77980-cpg-mssr: fix RPC-IF module clock's parent Sergei Shtylyov
@ 2019-09-27 18:09 ` Sergei Shtylyov
  2019-10-07 11:45   ` Geert Uytterhoeven
  6 siblings, 1 reply; 17+ messages in thread
From: Sergei Shtylyov @ 2019-09-27 18:09 UTC (permalink / raw)
  To: linux-renesas-soc, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
clk_register_composite() when registering the RPC[D2] clocks...

Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
This patch is against the 'clk-renesas' branch of Geert Uytterhoeven's
'renesas-drivers.git' repo.

 drivers/clk/renesas/rcar-gen3-cpg.c |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Index: renesas/drivers/clk/renesas/rcar-gen3-cpg.c
===================================================================
--- renesas.orig/drivers/clk/renesas/rcar-gen3-cpg.c
+++ renesas/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -464,7 +464,8 @@ static struct clk * __init cpg_rpc_clk_r
 
 	clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
 				     &rpc->div.hw,  &clk_divider_ops,
-				     &rpc->gate.hw, &clk_gate_ops, 0);
+				     &rpc->gate.hw, &clk_gate_ops,
+				     CLK_SET_RATE_PARENT);
 	if (IS_ERR(clk)) {
 		kfree(rpc);
 		return clk;
@@ -500,7 +501,8 @@ static struct clk * __init cpg_rpcd2_clk
 
 	clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
 				     &rpcd2->fixed.hw, &clk_fixed_factor_ops,
-				     &rpcd2->gate.hw, &clk_gate_ops, 0);
+				     &rpcd2->gate.hw, &clk_gate_ops,
+				     CLK_SET_RATE_PARENT);
 	if (IS_ERR(clk))
 		kfree(rpcd2);
 

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH] clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks
  2019-09-27 18:09 ` [PATCH] clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks Sergei Shtylyov
@ 2019-10-07 11:45   ` Geert Uytterhoeven
  2019-10-07 11:49     ` Sergei Shtylyov
  2019-12-20 14:31     ` Geert Uytterhoeven
  0 siblings, 2 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2019-10-07 11:45 UTC (permalink / raw)
  To: Sergei Shtylyov
  Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

Hi Sergei,

On Fri, Sep 27, 2019 at 8:09 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
> and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
> clk_register_composite() when registering the RPC[D2] clocks...
>
> Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Thanks for your patch!

LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Now, before I apply this: does this make RPC-IF work?

> --- renesas.orig/drivers/clk/renesas/rcar-gen3-cpg.c
> +++ renesas/drivers/clk/renesas/rcar-gen3-cpg.c
> @@ -464,7 +464,8 @@ static struct clk * __init cpg_rpc_clk_r
>
>         clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
>                                      &rpc->div.hw,  &clk_divider_ops,
> -                                    &rpc->gate.hw, &clk_gate_ops, 0);
> +                                    &rpc->gate.hw, &clk_gate_ops,
> +                                    CLK_SET_RATE_PARENT);
>         if (IS_ERR(clk)) {
>                 kfree(rpc);
>                 return clk;
> @@ -500,7 +501,8 @@ static struct clk * __init cpg_rpcd2_clk
>
>         clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
>                                      &rpcd2->fixed.hw, &clk_fixed_factor_ops,
> -                                    &rpcd2->gate.hw, &clk_gate_ops, 0);
> +                                    &rpcd2->gate.hw, &clk_gate_ops,
> +                                    CLK_SET_RATE_PARENT);
>         if (IS_ERR(clk))
>                 kfree(rpcd2);

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH] clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks
  2019-10-07 11:45   ` Geert Uytterhoeven
@ 2019-10-07 11:49     ` Sergei Shtylyov
  2019-12-17 20:43       ` Geert Uytterhoeven
  2019-12-20 14:31     ` Geert Uytterhoeven
  1 sibling, 1 reply; 17+ messages in thread
From: Sergei Shtylyov @ 2019-10-07 11:49 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

On 10/07/2019 02:45 PM, Geert Uytterhoeven wrote:

>> I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
>> and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
>> clk_register_composite() when registering the RPC[D2] clocks...
>>
>> Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> 
> Thanks for your patch!
> 
> LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

   Thanks. :-)

> Now, before I apply this: does this make RPC-IF work?

   Unfortunately, no. :-/

MBR, Sergei

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH] clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks
  2019-10-07 11:49     ` Sergei Shtylyov
@ 2019-12-17 20:43       ` Geert Uytterhoeven
  2019-12-18 19:34         ` Sergei Shtylyov
  0 siblings, 1 reply; 17+ messages in thread
From: Geert Uytterhoeven @ 2019-12-17 20:43 UTC (permalink / raw)
  To: Sergei Shtylyov
  Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

Hi Sergei,

On Mon, Oct 7, 2019 at 1:49 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> On 10/07/2019 02:45 PM, Geert Uytterhoeven wrote:
> >> I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
> >> and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
> >> clk_register_composite() when registering the RPC[D2] clocks...
> >>
> >> Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >
> > Thanks for your patch!
> >
> > LGTM, so
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
>    Thanks. :-)
>
> > Now, before I apply this: does this make RPC-IF work?
>
>    Unfortunately, no. :-/

As per private communication, I understand the problem is elsewhere,
and this patch itself is working fine, and thus safe to apply?

Thanks for confirming!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH] clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks
  2019-12-17 20:43       ` Geert Uytterhoeven
@ 2019-12-18 19:34         ` Sergei Shtylyov
  0 siblings, 0 replies; 17+ messages in thread
From: Sergei Shtylyov @ 2019-12-18 19:34 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

On 12/17/2019 11:43 PM, Geert Uytterhoeven wrote:

[...]
>>>> I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
>>>> and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
>>>> clk_register_composite() when registering the RPC[D2] clocks...
>>>>
>>>> Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>>
>>> Thanks for your patch!
>>>
>>> LGTM, so
>>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>
>>    Thanks. :-)
>>
>>> Now, before I apply this: does this make RPC-IF work?
>>
>>    Unfortunately, no. :-/
> 
> As per private communication, I understand the problem is elsewhere,
> and this patch itself is working fine, and thus safe to apply?

   Yes, I was able to lower the RPC[D2] frequencies but that didn't
really help...
   I should mention that CLK_SET_RATE_PARENT logic seemed a bit backward
to me, i.e. how the given clock know the properties of its parent clock...

> Thanks for confirming!
> 
> Gr{oetje,eeting}s,
> 
>                         Geert

MBR, Sergei

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH] clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks
  2019-10-07 11:45   ` Geert Uytterhoeven
  2019-10-07 11:49     ` Sergei Shtylyov
@ 2019-12-20 14:31     ` Geert Uytterhoeven
  1 sibling, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2019-12-20 14:31 UTC (permalink / raw)
  To: Sergei Shtylyov
  Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
	Geert Uytterhoeven, linux-clk

On Mon, Oct 7, 2019 at 1:45 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Fri, Sep 27, 2019 at 8:09 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
> > and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
> > clk_register_composite() when registering the RPC[D2] clocks...
> >
> > Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Thanks for your patch!
>
> LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Queueing in clk-renesas-for-v5.6.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 17+ messages in thread

end of thread, other threads:[~2019-12-20 14:31 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-22 19:55 [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Sergei Shtylyov
2019-01-22 19:57 ` [PATCH v3 1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify() Sergei Shtylyov
2019-01-22 19:58 ` [PATCH v3 2/4] clk: renesas: rcar-gen3-cpg: add spinlock Sergei Shtylyov
2019-01-22 19:59 ` [PATCH v3 3/4] clk: renesas: rcar-gen3-cpg: add RPC clocks Sergei Shtylyov
2019-01-25 10:25   ` Geert Uytterhoeven
2019-01-22 20:01 ` [PATCH v3 4/4] clk: renesas: r8a77980-cpg-mssr: " Sergei Shtylyov
2019-01-25 10:25 ` [PATCH v3 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Geert Uytterhoeven
2019-03-07 19:53 ` [PATCH] clk: renesas: r8a77980-cpg-mssr: fix RPC-IF module clock's parent Sergei Shtylyov
2019-03-11  9:30   ` Geert Uytterhoeven
2019-03-11 17:14     ` Sergei Shtylyov
2019-03-11 19:10       ` Sergei Shtylyov
2019-09-27 18:09 ` [PATCH] clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks Sergei Shtylyov
2019-10-07 11:45   ` Geert Uytterhoeven
2019-10-07 11:49     ` Sergei Shtylyov
2019-12-17 20:43       ` Geert Uytterhoeven
2019-12-18 19:34         ` Sergei Shtylyov
2019-12-20 14:31     ` Geert Uytterhoeven

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