From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: Linus Walleij <linus.walleij@linaro.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Subject: [PATCH] pinctrl: sh-pfc: r8a77970: fix pin I/O voltage control support
Date: Wed, 18 Apr 2018 23:06:30 +0300 [thread overview]
Message-ID: <fbb024c5-4451-22ce-8f2a-660ce618c861@cogentembedded.com> (raw)
In-Reply-To: <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com>
I've included the pin I/O voltage control into the R8A77970 PFC driver but
it was incomplete because:
- SH_PFC_PIN_CFG_IO_VOLTAGE pin flags weren't set properly;
- sh_pfc_soc_info::ioctrl_regs wasn't set at all...
Fixes: b92ac66a181 ("pinctrl: sh-pfc: Add R8A77970 PFC support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
The patch is against the 'sh-pfc' branch of Geert's 'renesas-drivers.git' repo.
drivers/pinctrl/sh-pfc/pfc-r8a77970.c | 34 ++++++++++++++++++++++++++--------
1 file changed, 26 insertions(+), 8 deletions(-)
Index: renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
===================================================================
--- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
@@ -21,13 +21,15 @@
#include "core.h"
#include "sh_pfc.h"
+#define CFG_FLAGS SH_PFC_PIN_CFG_DRIVE_STRENGTH
+
#define CPU_ALL_PORT(fn, sfx) \
- PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
- PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
- PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
- PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
- PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
- PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
+ PORT_GP_CFG_22(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_6(4, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_15(5, fn, sfx, CFG_FLAGS)
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
@@ -2382,18 +2384,33 @@ static const struct pinmux_cfg_reg pinmu
{ },
};
+enum ioctrl_regs {
+ IOCTRL30,
+ IOCTRL31,
+ IOCTRL32,
+ IOCTRL40,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+ [IOCTRL30] = { 0xe6060380 },
+ [IOCTRL31] = { 0xe6060384 },
+ [IOCTRL32] = { 0xe6060388 },
+ [IOCTRL40] = { 0xe60603c0 },
+ { /* sentinel */ },
+};
+
static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
u32 *pocctrl)
{
int bit = pin & 0x1f;
- *pocctrl = 0xe6060380;
+ *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
return bit;
if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
return bit + 22;
- *pocctrl += 4;
+ *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
return bit - 10;
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
@@ -2421,6 +2438,7 @@ const struct sh_pfc_soc_info r8a77970_pi
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
+ .ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
next prev parent reply other threads:[~2018-04-18 20:06 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-08 19:10 [PATCH v2 0/2] Add Renesas R8A77980 PFC driver Sergei Shtylyov
2018-03-08 19:12 ` [PATCH v2 1/2] pinctrl: sh-pfc: add PORT_GP_CFG_25() helper macro Sergei Shtylyov
2018-03-08 19:14 ` [PATCH v2 2/2] pinctrl: sh-pfc: add R8A77980 PFC support Sergei Shtylyov
2018-03-09 12:14 ` Geert Uytterhoeven
2018-03-13 19:54 ` [PATCH] pinctrl: sh-pfc: r8a77970: add EtherAVB pin groups Sergei Shtylyov
2018-03-14 13:41 ` Geert Uytterhoeven
2018-04-13 18:29 ` [PATCH] pinctrl: sh-pfc: r8a77970: add pin I/O voltage control Sergei Shtylyov
2018-04-13 18:31 ` Sergei Shtylyov
2018-04-13 18:33 ` Sergei Shtylyov
2018-04-16 13:02 ` Geert Uytterhoeven
2018-04-16 15:06 ` Sergei Shtylyov
2018-04-17 7:42 ` Geert Uytterhoeven
2018-04-19 12:54 ` Geert Uytterhoeven
2018-04-18 20:06 ` Sergei Shtylyov [this message]
2018-04-18 20:20 ` [PATCH] pinctrl: sh-pfc: r8a77970: fix pin I/O voltage control support Sergei Shtylyov
2018-04-18 20:26 ` [PATCH v2] " Sergei Shtylyov
2018-04-19 13:06 ` Geert Uytterhoeven
2018-04-19 16:03 ` Sergei Shtylyov
2018-04-19 16:03 ` Sergei Shtylyov
2018-04-19 18:27 ` [PATCH v2] pinctrl: sh-pfc: r8a77980: add " Sergei Shtylyov
2018-04-24 10:22 ` Geert Uytterhoeven
2018-04-19 18:52 ` [PATCH v3] pinctrl: sh-pfc: r8a77970: fix " Sergei Shtylyov
2018-04-24 10:22 ` Geert Uytterhoeven
2018-11-06 18:52 ` [PATCH] pinctrl: sh-pfc: r8a77970: add QSPI pins, groups, and functions Sergei Shtylyov
2018-11-07 11:12 ` Simon Horman
2018-11-08 13:11 ` Geert Uytterhoeven
2018-11-19 17:30 ` [PATCH] pinctrl: sh-pfc: r8a77980: " Sergei Shtylyov
2018-11-20 8:27 ` Geert Uytterhoeven
2020-06-05 20:23 ` [PATCH] pinctrl: sh-pfc: r8a77980: add RPC " Sergei Shtylyov
2020-06-08 12:58 ` Geert Uytterhoeven
2020-06-18 19:46 ` [PATCH] pinctrl: sh-pfc: r8a77970: " Sergei Shtylyov
2020-06-19 12:58 ` Geert Uytterhoeven
2020-06-19 15:23 ` Sergei Shtylyov
2020-06-19 17:54 ` Sergei Shtylyov
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