On Wed, 20 Feb 2019, Björn Töpel wrote:

> I noticed that RISC-V currently uses the generic one. Has there been
> any work on moving to a RISC-V specific impl, based on the
> A-extensions, similar to what aarch64 does? Would that make sense?

arm64 does not really handle that effectively. Intel has a single
instruction to increment a counter without requiring full consistency
guarantees like full blown atomics. The single instruction is important
to guarantee that the processing cannot be interrupted and thus there is
no need to disable preemption or interrupts.

What you want is some special instruction that can be executed in a cycle
or so and dedicate a register to the per cpu base address (comparable to
the
segment register on intel) so that you can do

	inc [per cpu register + offset]

in one cycle on an arbitrary hardware thread. That way you can keep
statistics effectvely and without contention. The vmstat subsystem is
based on that.