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From: Logan Gunthorpe <logang@deltatee.com>
To: Paul Walmsley <paul.walmsley@sifive.com>
Cc: "sorear2@gmail.com" <sorear2@gmail.com>,
	"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
	"alex@ghiti.fr" <alex@ghiti.fr>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"Palmer Dabbelt \( Sifive\)" <palmer@g.sifive.com>,
	"Anup.Patel@wdc.com" <Anup.Patel@wdc.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"Paul Walmsley \( Sifive\)" <paul.walmsley@g.sifive.com>,
	"rppt@linux.ibm.com" <rppt@linux.ibm.com>,
	Sachin Ghadi <sachin.ghadi@sifive.com>,
	Yash Shah <yash.shah@sifive.com>,
	Greentime Hu <greentime.hu@g.sifive.com>,
	"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"will@kernel.org" <will@kernel.org>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"allison@lohutok.net" <allison@lohutok.net>
Subject: Re: [PATCH] RISC-V: Add PCIe I/O BAR memory mapping
Date: Thu, 24 Oct 2019 11:07:12 -0600	[thread overview]
Message-ID: <0684fa31-1dfd-9f6c-762e-5811e6e9d5b9@deltatee.com> (raw)
In-Reply-To: <alpine.DEB.2.21.9999.1910240937350.20010@viisi.sifive.com>



On 2019-10-24 10:51 a.m., Paul Walmsley wrote:
> On Thu, 24 Oct 2019, Logan Gunthorpe wrote:
> 
>> On 2019-10-24 3:14 a.m., Yash Shah wrote:
>>> For I/O BARs to work correctly on RISC-V Linux, we need to establish a
>>> reserved memory region for them, so that drivers that wish to use I/O BARs
>>> can issue reads and writes against a memory region that is mapped to the
>>> host PCIe controller's I/O BAR MMIO mapping.
>>
>> I don't think other arches do this. 
> 
> $ git grep 'define PCI_IOBASE' arch/ 
> arch/arm/include/asm/io.h:#define PCI_IOBASE            ((void __iomem *)PCI_IO_VIRT_BASE)
> arch/arm64/include/asm/io.h:#define PCI_IOBASE          ((void __iomem *)PCI_IO_START)
> arch/m68k/include/asm/io_no.h:#define PCI_IOBASE        ((void __iomem *) PCI_IO_PA)
> arch/microblaze/include/asm/io.h:#define PCI_IOBASE     ((void __iomem *)_IO_BASE)
> arch/unicore32/include/asm/io.h:#define PCI_IOBASE      PKUNITY_PCILIO_BASE
> arch/xtensa/include/asm/io.h:#define PCI_IOBASE         ((void __iomem *)XCHAL_KIO_BYPASS_VADDR)
> $
> 
> This is for the old x86-style, non-memory mapped I/O address space the 
> legacy PCI stuff that one would use in{b,w,l}()/out{b,w,l}() for.
> 
> Yash, you might consider updating your patch description to note that this 
> is for "legacy I/O BARs (i.e., non-MMIO BARs)" or something similar.  That 
> might make things clearer.

Ah, right, yes, that would clear things up.

Logan

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  reply	other threads:[~2019-10-24 17:07 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-24  9:14 [PATCH] RISC-V: Add PCIe I/O BAR memory mapping Yash Shah
2019-10-24 16:24 ` Logan Gunthorpe
2019-10-24 16:51   ` Paul Walmsley
2019-10-24 17:07     ` Logan Gunthorpe [this message]
2019-10-25  6:35     ` Yash Shah

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