From mboxrd@z Thu Jan 1 00:00:00 1970 From: jhugo@codeaurora.org (Jeffrey Hugo) Date: Thu, 15 Nov 2018 11:31:33 -0700 Subject: [RFC 0/3] Unify CPU topology across ARM64 & RISC-V In-Reply-To: <1541728209-3224-1-git-send-email-atish.patra@wdc.com> References: <1541728209-3224-1-git-send-email-atish.patra@wdc.com> Message-ID: <07d92dd4-f943-47ee-e168-46bfaf4ed755@codeaurora.org> To: linux-riscv@lists.infradead.org List-Id: linux-riscv.lists.infradead.org On 11/8/2018 6:50 PM, Atish Patra wrote: > The cpu-map DT entry in ARM64 can describe the CPU topology in > much better way compared to other existing approaches. RISC-V can > easily adopt this binding to represent it's own CPU topology. > Thus, both cpu-map DT binding and topology parsing code can be > moved to a common location so that RISC-V or any other > architecture can leverage that. > > The relevant discussion regarding unifying cpu topology can be > found in [1]. > > arch_topology seems to be a perfect place to move the common > code. I have not introduced any functional changes in the moved > to code. The only downside in this approach is that the capacity > code will be executed for RISC-V as well. But, it will exit > immediately after not able to find the appropriate DT node. If > the overhead is considered too much, we can always compile out > capacity related functions under a different config for the > architectures that do not support them. > > The patches have been tested for RISC-V and compile tested for > ARM64. > > The socket changes[2] can be merged on top of this series or vice > versa. > > [1] https://lkml.org/lkml/2018/11/6/19 > [2] https://lkml.org/lkml/2018/11/7/918 > > Atish Patra (3): > dt-binding: cpu-topology: Move cpu-map to a common binding. > cpu-topology: Move cpu topology code to common code. > RISC-V: Parse cpu topology during boot. > > Documentation/devicetree/bindings/arm/topology.txt | 475 ------------------- > .../devicetree/bindings/cpu/cpu-topology.txt | 526 +++++++++++++++++++++ > arch/arm64/include/asm/topology.h | 23 +- > arch/arm64/kernel/topology.c | 305 +----------- > arch/riscv/Kconfig | 1 + > arch/riscv/kernel/smpboot.c | 6 +- > drivers/base/arch_topology.c | 303 ++++++++++++ > include/linux/arch_topology.h | 23 + > include/linux/topology.h | 1 + > 9 files changed, 864 insertions(+), 799 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/arm/topology.txt > create mode 100644 Documentation/devicetree/bindings/cpu/cpu-topology.txt > I was interested in testing these on QDF2400, an ARM64 platform, since this series touches core ARM64 code and I'd hate to see a regression. However, I can't figure out what baseline to use to apply these. Different patches cause different conflicts of a variety of baselines I attempted. What are these intended to apply to? Also, you might want to run them through checkpatch next time. There are several whitespace errors. -- Jeffrey Hugo Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. 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Thu, 15 Nov 2018 18:31:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1542306694; bh=jpEIkjvcZ8jlQzVWhG3nb8LE1eYiqzJG4XzJilQuduI=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=QKu1W79eS6Bw8yuhfurqGZFSHwzm/7sD/nYeABUsCmytWancBGfZ6zLl2EvyszIyd zX5w9mkzJJaO+prs6AEWlVgKsn1jNkoZ58EchcUTq2w4dwishZ12L2ze90yQ0U3WCw pGo2DvmiAn2FUcL1QafDrEo8TfMrYqzA4pmAvftY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 909E96044B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jhugo@codeaurora.org Subject: Re: [RFC 0/3] Unify CPU topology across ARM64 & RISC-V To: Atish Patra , linux-kernel@vger.kernel.org References: <1541728209-3224-1-git-send-email-atish.patra@wdc.com> From: Jeffrey Hugo Message-ID: <07d92dd4-f943-47ee-e168-46bfaf4ed755@codeaurora.org> Date: Thu, 15 Nov 2018 11:31:33 -0700 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <1541728209-3224-1-git-send-email-atish.patra@wdc.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181115_183150_780883_CE1C4B11 X-CRM114-Status: GOOD ( 25.58 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Damien.LeMoal@wdc.com, juri.lelli@arm.com, anup@brainfault.org, palmer@sifive.com, jeremy.linton@arm.com, robh+dt@kernel.org, sudeep.holla@arm.com, mick@ics.forth.gr, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org Message-ID: <20181115183133.ek03hSxJIRLj5o9AG6jdZegEz5z3YxiOH8SFQatTnqk@z> On 11/8/2018 6:50 PM, Atish Patra wrote: > The cpu-map DT entry in ARM64 can describe the CPU topology in > much better way compared to other existing approaches. RISC-V can > easily adopt this binding to represent it's own CPU topology. > Thus, both cpu-map DT binding and topology parsing code can be > moved to a common location so that RISC-V or any other > architecture can leverage that. > > The relevant discussion regarding unifying cpu topology can be > found in [1]. > > arch_topology seems to be a perfect place to move the common > code. I have not introduced any functional changes in the moved > to code. The only downside in this approach is that the capacity > code will be executed for RISC-V as well. But, it will exit > immediately after not able to find the appropriate DT node. If > the overhead is considered too much, we can always compile out > capacity related functions under a different config for the > architectures that do not support them. > > The patches have been tested for RISC-V and compile tested for > ARM64. > > The socket changes[2] can be merged on top of this series or vice > versa. > > [1] https://lkml.org/lkml/2018/11/6/19 > [2] https://lkml.org/lkml/2018/11/7/918 > > Atish Patra (3): > dt-binding: cpu-topology: Move cpu-map to a common binding. > cpu-topology: Move cpu topology code to common code. > RISC-V: Parse cpu topology during boot. > > Documentation/devicetree/bindings/arm/topology.txt | 475 ------------------- > .../devicetree/bindings/cpu/cpu-topology.txt | 526 +++++++++++++++++++++ > arch/arm64/include/asm/topology.h | 23 +- > arch/arm64/kernel/topology.c | 305 +----------- > arch/riscv/Kconfig | 1 + > arch/riscv/kernel/smpboot.c | 6 +- > drivers/base/arch_topology.c | 303 ++++++++++++ > include/linux/arch_topology.h | 23 + > include/linux/topology.h | 1 + > 9 files changed, 864 insertions(+), 799 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/arm/topology.txt > create mode 100644 Documentation/devicetree/bindings/cpu/cpu-topology.txt > I was interested in testing these on QDF2400, an ARM64 platform, since this series touches core ARM64 code and I'd hate to see a regression. However, I can't figure out what baseline to use to apply these. Different patches cause different conflicts of a variety of baselines I attempted. What are these intended to apply to? Also, you might want to run them through checkpatch next time. There are several whitespace errors. -- Jeffrey Hugo Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv